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(R)
RIVA 128ZXTM
128-BIT 3D MULTIMEDIA ACCELERATOR
PRELIMINARY DATA
KEY FEATURES * Fast 32-bit VGA/SVGA * High performance 128-bit 2D/GUI/DirectDraw Acceleration * Interactive, Photorealistic Direct3D Acceleration with advanced effects * Pinout backwards compatible with RIVA 128 * Massive 1.6Gbytes/s, 100MHz 128-bit wide 8MByte SGRAM framebuffer interface * Adds 16Mbit SDRAM support for cost sensitive 8MByte framebuffer applications * Video Acceleration for DirectDraw/DirectVideo, MPEG-1/2 and Indeo(R) - Planar 4:2:0 and packed 4:2:2 Color Space Conversion - X and Y smooth up and down scaling * 250MHz Palette-DAC supporting up to 1600x1200@85Hz * NTSC and PAL output with flicker-filter * Multi-function Video Port and serial interface BLOCK DIAGRAM
* Bus mastering DMA Accelerated Graphics Port
(AGP) 1.0 Interface supporting 133MHz 2X data transfer mode
* Bus mastering DMA PCI 2.1 interface * ACPI power management interface support * 0.35 micron 5LM CMOS * 300 PBGA
DESCRIPTION The RIVA128ZXTM offers unparalleled 2D and 3D performance, meeting all the requirements of the mainstream PC graphics market and Microsoft's PC'97. RIVA128ZX combines all the features of RIVA 128 plus 8MByte SDRAM and SGRAM based framestore support and AGP 2X data transfer. It provides the most advanced Direct3DTM acceleration solution and delivers leadership VGA, 2D and Video performance, enabling a range of applications from 3D games through to DVD, IntercastTM and video conferencing.
1.6 GByte/s Internal Bus Bandwidth
DMA Bus
Video Port
DMA Engine
CCIR656 Video
PCI/AGP
Host Interface
FIFO/ DMA Pusher
Graphics Engine 128 bit 2D Direct3D
DMA Engine
Internal Bus
Palette DAC YUV - RGB, X & Y scaler 8MByte SDRAM/SGRAM Interface
Monitor/ TV
VGA
128 bit interface
June 1998 The information in this datasheet is subject to change
7071857 00 1/85
RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
TABLE OF CONTENTS 1 2 RIVA128ZX 300PBGA DEVICE PINOUT....................................................................................... PIN DESCRIPTIONS ...................................................................................................................... 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE ..................................................... 2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................ 2.3 FRAMEBUFFER INTERFACE .............................................................................................. 2.4 VIDEO PORT......................................................................................................................... 2.5 DEVICE ENABLE SIGNALS .................................................................................................. 2.6 DISPLAY INTERFACE .......................................................................................................... 2.7 VIDEO DAC AND PLL ANALOG SIGNALS .......................................................................... 2.8 POWER SUPPLY .................................................................................................................. 2.9 TEST...................................................................................................................................... OVERVIEW OF THE RIVA128ZX .................................................................................................. 3.1 BALANCED PC SYSTEM...................................................................................................... 3.2 HOST INTERFACE ............................................................................................................... 3.3 2D ACCELERATION ............................................................................................................. 3.4 3D ENGINE ........................................................................................................................... 3.5 VIDEO PROCESSOR............................................................................................................ 3.6 VIDEO PORT......................................................................................................................... 3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER ......................................... 3.8 SUPPORT FOR STANDARDS.............................................................................................. 3.9 RESOLUTIONS SUPPORTED.............................................................................................. 3.10 CUSTOMER EVALUATION KIT ............................................................................................ 3.11 TURNKEY MANUFACTURING PACKAGE ........................................................................... ACCELERATED GRAPHICS PORT (AGP) INTERFACE ............................................................. 4.1 RIVA128ZX AGP INTERFACE .............................................................................................. 4.2 AGP BUS TRANSACTIONS.................................................................................................. PCI 2.1 LOCAL BUS INTERFACE................................................................................................. 5.1 RIVA128ZX PCI INTERFACE ............................................................................................... 5.2 PCI TIMING SPECIFICATION ............................................................................................... FRAMEBUFFER INTERFACE ....................................................................................................... 6.1 SDRAM INTERFACE ............................................................................................................ 6.2 SGRAM INTERFACE ............................................................................................................ 6.3 SDRAM/SGRAM ACCESSES AND COMMANDS ................................................................ 6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................ 6.5 FRAMEBUFFER INTERFACE TIMING SPECIFICATION .................................................... VIDEO PLAYBACK ARCHITECTURE........................................................................................... 7.1 VIDEO SCALER PIPELINE ................................................................................................... VIDEO PORT .................................................................................................................................. 8.1 VIDEO INTERFACE PORT FEATURES ............................................................................... 8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC .............................. 8.3 TIMING DIAGRAMS .............................................................................................................. 8.4 656 MASTER MODE ............................................................................................................. 8.5 VBI HANDLING IN THE VIDEO PORT ................................................................................. 8.6 SCALING IN THE VIDEO PORT ........................................................................................... BOOT ROM INTERFACE............................................................................................................... 4 5 5 5 7 7 8 8 8 8 9 10 10 10 11 11 11 12 12 12 12 13 13 14 15 15 23 23 24 30 31 32 35 37 37 42 43 45 45 46 47 51 52 52 53
3
4
5
6
7 8
9
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128-BIT 3D MULTIMEDIA ACCELERATOR
10 11
RIVA128ZX
55 57 57 57 58 59 60 61 63 63 63 64 64 64 64 65 65 66 67 67 68 68 69 69 69
POWER-ON RESET CONFIGURATION........................................................................................ DISPLAY INTERFACE ................................................................................................................... 11.1 PALETTE-DAC ...................................................................................................................... 11.2 PIXEL MODES SUPPORTED ............................................................................................... 11.3 HARDWARE CURSOR ......................................................................................................... 11.4 SERIAL INTERFACE............................................................................................................. 11.5 ANALOG INTERFACE .......................................................................................................... 11.6 TV OUTPUT SUPPORT ........................................................................................................ IN-CIRCUIT BOARD TESTING ...................................................................................................... 12.1 TEST MODES ....................................................................................................................... 12.2 CHECKSUM TEST ................................................................................................................ ELECTRICAL SPECIFICATIONS .................................................................................................. 13.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................ 13.2 OPERATING CONDITIONS .................................................................................................. 13.3 DC SPECIFICATIONS........................................................................................................... 13.4 ELECTRICAL SPECIFICATIONS .......................................................................................... 13.5 DAC CHARACTERISTICS .................................................................................................... 13.6 FREQUENCY SYNTHESIS CHARACTERISTICS ................................................................ PACKAGE DIMENSION SPECIFICATION .................................................................................... 14.1 300 PIN BALL GRID ARRAY PACKAGE .............................................................................. REFERENCES................................................................................................................................
12
13
14 15
16 ORDERING INFORMATION .......................................................................................................... APPENDIX ............................................................................................................................................... A PCI CONFIGURATION REGISTERS ............................................................................................. A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE ....................................
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1
NOTES
RIVA128ZX
4/85 4
FBD[17] FBD[19] FBD[21] FBD[23] FBDQM[2] FBA[0] FBA[2] FBA[4] FBA[6] FBA[8] FBDQM[5] FBD[41] FBD[43] FBD[45] FBD[47] FBD[56] FBD[57]
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RIVA128ZX 300PBGA DEVICE PINOUT
1 2
FBD[18] FBD[20] FBD[22] FBDQM[0] FBA[9] FBA[1] FBA[3] FBA[5] FBA[7] FBCLK1 FBDQM[7] FBD[40] FBD[42] FBD[44] FBD[46] FBD[58] FBD[59] FBD[27] FBD[26] FBD[25] FBD[15] FBD[13] FBD[11] FBD[9] FBDQM[1] FBWE# FBRAS# FBA[10] FBDQM[4] FBD[55] FBD[54] FBD[53] FBD[60] FBD[61] FBD[30] VDD FBD[24] FBD[14] FBD[12] FBD[10] FBD[8] FBDQM[3] FBCAS# FBCS0 FBCS1 FBDQM[6] VDD FBD[52] FBD[51] FBD[62] FBD[63] VDD NIC VDD VDD VDD
A
FBD[4]
FBD[6]
FBD[7]
B
FBD[3]
FBD[5]
FBD[16]
C
FBD[1]
FBD[2]
FBD[28]
D
FBCKE
VDD VDD VDD VDD
FBCLK0
FBD[0]
FBD[29]
E
FBCLKFB VDD VDD FBD[48]
SCL
FBCLK2
FBD[31]
FBD[50]
FBD[39]
FBD[38]
F
MP_AD[4] MPCLAMP VDD
MP_AD[6]
NIC
SDA
FBD[49]
FBD[37]
FBD[36]
G
MP_AD[3] VDD
MPFRAME# MP_AD[7]
MP_AD[5]
FBD[35]
FBD[34]
FBD[33]
FBD[32]
H
MP_AD[0] GND GND GND GND
MP_AD[2]
MPSTOP#
MPCLK
NIC
FBDQM[12] FBDQM[14] FBDQM[15] FBDQM[13]
J
GND GND GND GND
FBDQM[8] MPDTACK# MP_AD[1]
FBD[118]
FBD[119]
FBD[105]
FBD[104]
K
FBD[73] GND GND GND GND
FBDQM[9]
FBD[87]
FBDQM[10] FBDQM[11]
FBD[116]
FBD[117]
FBD[107]
FBD[106]
L
FBD[75] GND GND GND GND
FBD[86]
FBD[85]
FBD[72]
FBD[114]
FBD[115]
FBD[109]
FBD[108]
M
FBD[77] NIC
FBD[84]
FBD[83]
FBD[74]
FBD[112]
FBD[113]
FBD[111]
FBD[110]
N
FBD[79] VDD
FBD[82]
FBD[81]
FBD[76]
NIC
FBD[102]
FBD[103]
FBD[121]
FBD[120]
P
FBD[89] NIC
FBD[80]
FBD[71]
FBD[78]
VDD
FBD[100]
FBD[101]
FBD[123]
FBD[122]
R
VDD NIC HOSTVDD HOSTVDD HOSTCLAMP
FBD[70]
FBD[69]
FBD[88]
NIC
FBD[98]
FBD[99]
FBD[125]
FBD[124]
T
FBD[91] HOSTCLAMP XTALOUT PCIRST# AGPST[1]
FBD[68]
FBD[67]
FBD[90]
HOSTVDD
HOSTCLAMP
HOSTVDD
HOSTCLAMP
VDD
FBD[97]
FBD[127]
FBD[126]
U
DACVDD VREF PCIINTA# PCIGNT#
FBD[66]
FBD[65]
FBD[92]
PCIAD[30] PCIAD[26] PCICBE#[3] PCIAD[20] PCIAD[16] PCITRDY#
PCIPAR
HOSTVDD PCICBE#[0]
FBD[96]
VIDVSYNC VIDHSYNC
V
COMP PLLVDD PCIREQ# AGPST[2]
FBD[64]
FBD[95]
RED
AGPPIPE# PCIAD[28] PCIAD[24] PCIAD[22]
PCIAD[18] PCIFRAME# PCISTOP# PCIAD[15] PCIAD[11]
PCIAD[6]
PCIAD[2] TESTMODE ROMCS#
W
XTALIN PCICLK AGPST[0]
FBD[93]
FBD[94]
BLUE
PCIAD[31] PCIAD[27]
AGPADSTB1
PCIAD[21]
PCIAD[17]
PCIIRDY# PCICBE#[1] PCIAD[13]
PCIAD[9]
PCIAD[4]
PCIAD[0]
PCIAD[7]
PCIAD[5]
NIC = No Internal Connection. Do not connect to these pins. VDD=3.3V Signals denoted with an asterisk are defined for future expansion. See Pin Descriptions, Section 2, page 5 for details.
PCIIDSEL/ PCIPCIAD[29] PCIAD[25] PCIAD[23] PCIAD[19] PCICBE#[2] AGPRBF# DEVSEL# PCIAD[14] PCIAD[12] PCIAD[10] PCIAD[8] AGPADSTB0 PCIAD[3] PCIAD[1]
128-BIT 3D MULTIMEDIA ACCELERATOR
Y
GREEN
GND
RSET
128-BIT 3D MULTIMEDIA ACCELERATOR
2 2.1 PIN DESCRIPTIONS ACCELERATED GRAPHICS PORT (AGP) INTERFACE
I/O I Description
RIVA128ZX
Signal AGPST[2:0]
AGP status bus providing information from the arbiter to the RIVA128ZX on what it may do. AGPST[2:0] only have meaning to the RIVA128ZX when PCIGNT# is asserted. When PCIGNT# is de-asserted these signals have no meaning and must be ignored. 000 001 010 011 100 101 110 111 Indicates that previously requested low priority read or flush data is being returned to the RIVA128ZX. Indicates that previously requested high priority read data is being returned to the RIVA128ZX. Indicates that the RIVA128ZX is to provide low priority write data for a previous enqueued write command. Indicates that the RIVA128ZX is to provide high priority write data for a previous enqueued write command. Reserved Reserved Reserved Indicates that the RIVA128ZX has been given permission to start a bus transaction. The RIVA128ZX may enqueue AGP requests by asserting AGPPIPE# or start a PCI transaction by asserting PCIFRAME#. AGPST[2:0] are always an output from the Core Logic (AGP chipset) and an input to the RIVA128ZX.
AGPRBF#
O
Read Buffer Full indicates when the RIVA128ZX is ready to accept previously requested low priority read data or not. When AGPRBF# is asserted the arbiter is not allowed to return (low priority) read data to the RIVA128ZX. This signal should be pulled up via a 4.7K resistor (although it is supposed to be pulled up by the motherboard chipset). Pipelined Read is asserted by RIVA128ZX (when the current master) to indicate a full width read address is to be enqueued by the target. The RIVA128ZX enqueues one request each rising clock edge while AGPPIPE# is asserted. When AGPPIPE# is deasserted no new requests are enqueued across PCIAD[31:0]. AGPPIPE# is a sustained tri-state signal from the RIVA128ZX and is an input to the target (the core logic). Bus strobe signals providing timing for AGP 2X data transfer mode on PCIAD[15:00] and PCIAD[31:16] respectively. The agent that is supplying data drives these signals.
AGPPIPE#
O
AGPADSTB0, AGPADSTB1
I/O
2.2
PCI 2.1 LOCAL BUS INTERFACE
I/O I Description PCI clock. This signal provides timing for all transactions on the PCI bus, except for PCIRST# and PCIINTA#. All PCI signals are sampled on the rising edge of PCICLK and all timing parameters are defined with respect to this edge . PCI reset. This signal is used to bring registers, sequencers and signals to a consistent state. When PCIRST# is asserted all output signals are tristated. 32-bit multiplexed address and data bus. A bus transaction consists of an address phase followed by one or more data phases.
Signal PCICLK
PCIRST# PCIAD[31:0]
I I/O
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RIVA128ZX
Signal PCICBE[3:0]# I/O I/O Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Multiplexed bus command and byte enable signals. During the address phase of a transaction PCICBE[3:0]# define the b us command, during the data phase PCICBE[3:0]# are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain valid data. PCICBE[0]# applies to byte 0 (LSB) and PCICBE[3]# applies to byte 3 (MSB). When connected to AGP these signals carry different commands than PCI when requests are being enqueued using AGPPIPE#. Valid byte information is provided during AGP write transactions. PCICBE[3:0]# are not used during the return of AGP read data. Parity. This signal is the even parity bit generated across PCIAD[31:0] and PCICBE[3:0]#. PCIPAR is stable and valid one clock after the address phase. For data phases PCIPAR is stable and valid one clock after either PCIIRDY# is asserted on a write transaction or PCITRDY# is asserted on a read transaction. Once PCIPAR is valid, it remains valid until one clock after completion of the current data phase. The master drives PCIPAR for address and write data phases; the target drives PCIPAR for read data phases. Cycle frame. This signal is driven by the current master to indicate the beginning of an access and its duration. PCIFRAME# is asserted to indicate that a bus transaction is beginning. Data transfers continue while PCIFRAME# is asserted. When PCIFRAME# is deasserted, the transaction is in the final data phase. Initiator ready. This signal indicates the initiator's (bus master's) ability to complete the current data phase of the transaction. See extended description for PCITRDY#. When connected to AGP this signal indicates the initiator (AGP compliant master) is ready to provide all write data for the current transaction. Once PCIIRDY# is asserted for a write operation, the master is not allowed to insert wait states. The assertion of PCIIRDY# for reads, indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers.
PCIPAR
I/O
PCIFRAME#
I/O
PCIIRDY#
I/O
PCITRDY#
I/O
Target ready. This signal indicates the target's (selected device's) ability to complete the current data phase of the transaction. PCITRDY# is used in conjunction with PCIIRDY#. A data phase is completed on any clock when both PCITRDY# and PCIIRDY# are sampled as being asserted. During a read, PCITRDY# indicates that valid data is present on PCIAD[31:0]. During a write, it indicates the target is prepared to accept data. Wait cycles are inserted until both PCIIRDY# and PCITRDY# are asserted together. When connected to AGP this signal indicates the AGP compliant target is ready to provide read data for the entire transaction (when transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data, when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfers on both read and write transactions.
PCISTOP# PCIIDSEL
I/O I
PCISTOP# indicates that the current target is requesting the master to terminate the current transaction. Initialization device select. This signal is used as a chip select during configuration read and write transactions. For AGP applications note that IDSEL is not a pin on the AGP connector. The RIVA128ZX performs the device select decode internally within its host interface. It is not required to connect the AD16 signal to the IDSEL pin as suggested in the AGP specification.
PCIDEVSEL#
I/O
Device select. When acting as an output PCIDEVSEL# indicates that the RIVA128ZX has decoded the PCI address and is claiming the current access as the target. As an input PCIDEVSEL# indicates whether any other device on the bus has been selected. Request. This signal is asserted by the RIVA128ZX to indicate to the arbiter that it desires to become master of the bus.
PCIREQ#
O
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128-BIT 3D MULTIMEDIA ACCELERATOR
Signal PCIGNT# I/O I Description
RIVA128ZX
Grant. This signal indicates to the RIVA128ZX that access to the bus has been granted and it can now become bus master. When connected to AGP additional information is provided on AGPST[2:0] indicating that the master is the recipient of previously requested read data (high or low priority), it is to provide write data (high or low priority), for a previously enqueued write command or has been given permission to start a bus transaction (AGP or PCI). Interrupt request line. This open drain output is asserted and deasserted asynchronously to PCICLK.
PCIINTA#
O
2.3
FRAMEBUFFER INTERFACE
I/O I/O Description The 128-bit memory data bus. FBD[31:0] are also used to access up to 64KBytes of 8-bit ROM or Flash ROM, using FBD[15:0] as address ROMA[15:0], FBD[31:24] as ROMD[7:0], FBD[17] as ROMWE# and FBD[16] as ROMOE#. Memory Address bus. Configur ation strapping options are also decoded on these signals during PCIRST# as described in Section 10, page 55. Memory Row Address Strobe for all memory devices. Memory Column Address Strobe for all memory devices. Memory Chip Select strobes. For SDRAM the FBCS[1] pin provides the memory's internal bank select bit (BA/A11). Memory Write Enable strobe for all memory devices. Memory Data/Output Enable strobes. Memory Clock signals. Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of memory for reduced clock skew and loading. Details of recommended memory clock layout are given in Section 6.4, page 37. Framebuffer clock feedback. FBCLK2 is fed back to FBCLKFB. Framebuffer memory clock enable signal.
Signal FBD[127:0]
FBA[10:0] FBRAS# FBCAS# FBCS[1:0]# FBWE# FBDQM[15:0] FBCLK0, FBCLK1, FBCLK2 FBCLKFB FBCKE
O O O O O O O
I O
2.4
VIDEO PORT
I/O I/O I I O I Description Media Port 8-bit multiplexed address and data bus or ITU-R-656 video data bus when in 656 mode. 40MHz Media Port system clock or pixel clock when in 656 mode. Media Port data transfer acknowledgment signal. Initiates Media Port transfers when active, terminates transfers when inactive. Media Port control signal used by the slave to terminate transfers.
Signal MP_AD[7:0] MPCLK MPDTACK# MPFRAME# MPSTOP#
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RIVA128ZX
2.5 DEVICE ENABLE SIGNALS
I/O O Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Signal ROMCS#
Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used in conjunction with framebuffer data lines as described above in Section 2.3.
2.6
DISPLAY INTERFACE
I/O I/O I/O O O Description Used for DDC2B+ monitor communication and interface to video decoder devices. Used for DDC2B+ monitor communication and interface to video decoder devices. Vertical sync supplied to the display monitor. No buffering is required. In TV mode this signal supplies composite sync to an external PAL/NTSC encoder. Horizontal sync supplied to the display monitor. No buffering is required.
Signal SDA SCL VIDVSYNC VIDHSYNC
2.7
VIDEO DAC AND PLL ANALOG SIGNALS
I/O O Description RGB display monitor outputs. These are software configur able to drive either a doubly terminated or singly terminated 75 load. External compensation capacitor for the video DACs. This pin should be connected to DACVDD via the compensation capacitor, see Figure 66, page 60. A precision resistor placed between this pin and GND sets the full-scale video DAC current, see Figure 66, page 60. A capacitor should be placed between this pin and GND as shown in Figure 66, page 60. A series resonant crystal is connected between these two points to provide the reference clock for the internal MCLK and VCLK clock synthesizers, see Figure 66 and Table 20, page 60. Alternately, an external LVTTL clock oscillator output may be driven into XTALOUT, connecting XTALIN to GND. For designs supporting TV-out, XTALOUT should be driven by a reference clock as described in Section 11.6, page 61.
Signal RED, GREEN, BLUE COMP RSET VREF XTALIN XTALOUT
I O
2.8
POWER SUPPLY
I/O P P P P P P Description Analog power supply for the video DACs. Analog power supply for all clock synthesizers. Digital power supply. Ground. MPCLAMP is connected to +5V to protect the 3.3V RIVA128ZX from external devices which will potentially drive 5V signal levels onto the Video Port input pins. HOSTVDD is connected to the Vddq 3.3 pins on the AGP connector. This is the supply voltage for the I/O buffers and is isolated from the core VDD. On AGP designs these pins are also connected to the HOSTCLAMP pins. On PCI designs they are connected to the 3.3V supply. HOSTCLAMP is the supply signalling rail protection for the host interface. In AGP designs these signals are connected to Vddq 3.3. For PCI designs they are connected to the I/O power pins (V(I/O)).
Signal DACVDD PLLVDD VDD GND MPCLAMP HOSTVDD
HOSTCLAMP
P
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128-BIT 3D MULTIMEDIA ACCELERATOR
2.9 TEST
I/O I Description
RIVA128ZX
Signal TESTMODE
For designs which will be tested in-circuit, this pin should be connected to GND through a 10K pull-down resistor, otherwise this pin should be connected directly to GND. When TESTMODE is asserted, MP_AD[3:0] are reassigned as TESTCTL[3:0] respectively. Information on in-circuit test is given in Section 12, page 63.
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RIVA128ZX
3 OVERVIEW OF THE RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
AGP accesses offer other performance enhancements since they are from non-cacheable memory (no snoop) and can be low priority to prevent processor stalls, or high priority to prevent graphics engine stalls. Building a balanced system RIVA128ZX is architected to provide the level of 3D graphics performance and quality available in top arcade platforms. To provide comparable scene complexity in the 1997 time-frame, processors will have to achieve new levels of floating point performance. Profiles have shown that 1997 mainstream CPUs will be able to transform over 1 million lit, meshed triangles/s at 50% utilization using Direct3D. This represents an order of magnitude performance increase over anything attainable in 1996 PC games. To build a balanced system the graphics pipeline must match the CPU's performance. It must be capable of rendering at least 1 million polygons/s in order to avoid CPU stalls. Factors affecting this system balance include:
* Direct3D compatibility. Minimizing the differ-
The RIVA128ZX is the first 128-bit 3D Multimedia Accelerator to offer unparalleled 2D and 3D performance, meeting all the requirements of the mainstream PC graphics market and Microsoft's PC'97. The RIVA128ZX introduces the most advanced Direct3DTM acceleration solution and also delivers leadership VGA, 2D and Video performance, enabling a range of applications from 3D games through to DVD, IntercastTM and video conferencing. 3.1 BALANCED PC SYSTEM
The RIVA128ZX is designed to leverage existing PC system resources such as system memory, high bandwidth internal buses and bus master capabilities. The synergy between the RIVA128ZX graphics pipeline architecture and that of the current generation PCI and next generation AGP platforms, defines ground breaking performance levels at the cost point currently required for mainstream PC graphics solutions. Execute versus DMA models The RIVA128ZX is architected to optimize PC system resources in a manner consistent with the AGP "Execute" model. In this model texture map data for 3D applications is stored in system memory and individual texels are accessed as needed by the graphics pipeline. This is a significant enhancement over the DMA model where entire texture maps are transferred into off-screen framebuffer memory. The advantages of the Execute versus the DMA model are: * Improved system performance since only the required texels and not the entire texture map, cross the bus. * Substantial cost savings since all the framebuffer is usable for the displayed screen and Z buffer and no part of it is required to be dedicated to texture storage or texture caching. * There is no software overhead in the Direct3D driver to manage texture caching between application memory and the framebuffer. To extend the advantages of the Execute model, the RIVA128ZX's proprietary texture cache and virtual DMA bus master design overcomes the bandwidth limitation of PCI, by sustaining a high texel throughput with minimum bus utilization. The host interface supports burst transactions up to 133MHz and provides over 400MBytes/s on AGP.
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ences between the hardware interface and the Direct3D data structures.
* Triangle setup. Minimizing the number of for-
mat conversions and delta calculations done by the CPU.
* Display-list processing. Avoiding CPU stalls by
allowing the graphics pipeline to execute independently of the CPU.
* Vertex caching. Avoids saturating the host in-
terface with repeated vertices, lowering the traffic on the bus and reducing system memory collisions.
* Host interface performance.
3.2
HOST INTERFACE
The host interface boosts communication between the host CPU and the RIVA128ZX. The optimized interface performs burst DMA bus mastering for efficient and fast data transfer.
* 32-bit PCI version 2.1 or AGP version 1.0 * Burst DMA Master and target * 33MHz PCI clock rate, 66MHz AGP clock rate
and AGP 2X mode
* Supports over 100MBytes/s with 33MHz PCI to
over 400MBytes/s on AGP 2X mode
* Implements read buffer posting on AGP
128-BIT 3D MULTIMEDIA ACCELERATOR
* Fully supports the "Execute" model on both PCI
RIVA128ZX
fers to Direct3D or similar APIs advanced triangle rendering capabilities: * Rendering pipeline optimized for Microsoft's Direct3D API * Perspective correct true-color Gouraud lighting and texture mapping * Full 32-bit RGBA texture filter and Gouraud lighting pixel data path * Alpha blending for translucency and transparency * Sub-pixel accurate texture mapping * Internal pixel path: up to 24bits, alpha: up to 8 bits * Texture magnification filtering with high quality bilinear filtering without performance degradation * Texture minification filtering with MIP mapping without performance degradation * LOD MIP-mapping: filter shape is dynamically adjusted based on surface orientation * Texture sizes from 4 to 2048 texels in either U or V * Textures can be looped and paged in real time for texture animation * Perspective correct per-pixel fog for atmospheric effects * Perspective correct specular highlights * Multi buffering (Double, Triple, Quad buffering) for smooth 3D animation * Multipass rendering for environmental mapping and advanced texturing 3.5 VIDEO PROCESSOR
and AGP 3.3 2D ACCELERATION
The RIVA128ZX's 2D rendering engine delivers industry-leading Windows acceleration performance: * 100MHz 128-bit graphics engine optimized for single cycle operation into the 128-bit memory interface supporting up to 1.6GBytes/s * Acceleration functions optimized for minimal software overhead on key GDI calls * Extensive support for DirectDraw in Windows95 including optimized Direct Framebuffer (DFB) access with Write-combining * Accelerated primitives including BLT, transparent BLT, stretchBLT, points, lins, lines, polylines, polygons, fills, patterns, arbitrary rectangular clipping and improved text rendering * Pipeline optimized for multiple color depths including 8, 15, 24, and 30 bits per pixel * DMA Pusher allows the 2D graphics pipeline to load rendering methods optimizing RIVA128ZX/host multi-tasking * Execution of all 256 Raster Operations (as defined by Microsoft Windows) at 8, 15, 24 and 30-bit color depths * 15-bit hardware color cursor * Hardware color dithering * Multi buffering (Double, Triple, Quad buffering) for smooth animation 3.4 3D ENGINE
Triangle setup engine * Setup hardware optimized for Microsoft's Direct3D API * 5Gflop floating point geometry processor * Slope and setup calculations * Accepts IEEE Single Precision format used in Direct3D * Efficient vertex caching Rendering engine The RIVA128ZX Multimedia Accelerator integrates an orthodox 3D rendering pipeline and triangle setup function which not only fully utilizes the capabilities of the Accelerated Graphics Port, but also supports advanced texture mapped 3D over the PCI bus. The RIVA128ZX 3D pipeline of-
The RIVA128ZX Palette-DAC pipeline accelerates full-motion video playback, sustaining 30 frames per second while retaining the highest quality color resolution, implementing true bilinear filtering for scaled video, and compensating for filtering losses using edge enhancement algorithms. * Advanced support for DirectDraw (DirectVideo) in Windows 95 * Back-end hardware video scaling for video conferencing and playback * Hardware color space conversion (YUV 4:2:2 and 4:2:0) * Multi-tap X and Y filtering for superior image quality * Optional edge enhancement to retain video sharpness
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RIVA128ZX
* Support for scaled field interframing for reduced * * *
128-BIT 3D MULTIMEDIA ACCELERATOR
3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER
*
motion artifacts and reduced storage Per-pixel color keying Multiple video windows with hardware color space conversion and filtering Planar YUV12 (4:2:0) to/from packed (4:2:2) conversion for software MPEG acceleration and H.261 video conferencing applications Accelerated playback of industry standard codecs including MPEG-1/2, Indeo, Cinepak VIDEO PORT
The RIVA128ZX has also been designed to interface to a standard PAL or NTSC television via a low cost TV encoder chip. In PAL or NTSC display modes the interlaced output is internally flicker-filtered and CCIR/EIA compliant timing reference signals are generated. 3.8 SUPPORT FOR STANDARDS
* Multimedia support for MS-DOS, Windows
3.6
3.11, Windows 95, and Windows NT
* Acceleration for Windows 95 Direct APIs in-
The RIVA128ZX Multimedia Accelerator provides connectivity for video input devices such as Philips SAA7111A, ITT 3225 and Samsung KS0127 through an ITU-R-656 video input bus to DVD and MPEG2 decoders through bidirectional media port functionality. * Supported through VPE extensions to DirectDraw * Supports filtered down-scaling and decimation * Supports real time video capture via Bus Mastering DMA * Serial interface for decoder control 3.9 RESOLUTIONS SUPPORTED
Resolution BPP 4 8 16 32 8 16 32 8 16 32 8 16 32 8 16 32 8 16 32 8 16 8 16 16 2MByte 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 100Hz 85Hz -
cluding Direct3D, DirectDraw and DirectVideo
* VGA and SVGA: The RIVA128ZX has an in-
dustry standard 32-bit VGA core and BIOS support. In PCI configuration space the VGA can be enabled and disabled independently of the GUI.
* Glue-less Accelerated Graphics Port (AGP 1.0)
or PCI 2.1 bus interface
* ITU/CCIR-656 compatible video port * VESA DDC2B+, DPMS, VBE 2.0 supported
4MByte (128-bit) 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 100Hz 100Hz 100Hz 85Hz 85Hz 85Hz 75Hz -
8MByte (64-bit) 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 100Hz 100Hz 100Hz t.b.d. 85Hz 85Hz 85Hz 85Hz 75Hz 75Hz 60Hz
8MByte (128-bit) 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 120Hz 100Hz 100Hz 100Hz 75Hz 85Hz 85Hz 60Hz 85Hz 85Hz 75Hz 75Hz 60Hz
640x480
800x600
1024x768
1152x864
1280x1024
1600x1200
1920x1080 1920x1200 1800x1440
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128-BIT 3D MULTIMEDIA ACCELERATOR
3.10 CUSTOMER EVALUATION KIT A Customer Evaluation Kit (CEK) is available for evaluating the RIVA128ZX. The CEK includes a PCI or AGP adapter card designed to support the RIVA128ZX feature set, an evaluation CD-ROM containing a fast-installation application, extensive device drivers and programs demonstrating the RIVA128ZX features and performance. This CEK includes: * RIVA128ZX evaluation board and CD-ROM * QuickStart install/user guide * OS drivers and files - Windows 3.11 - Windows 95 Direct X/3D - Windows NT 3.5 - Windows NT 4.0 * Demonstration files and Game demos * Benchmark programs and files 3.11 TURNKEY MANUFACTURING PACKAGE A Turnkey Manufacturing Package (TMP) is available to support OEM designs and development through to production. It delivers a complete manufacturable hardware and software solution that
RIVA128ZX
allows an OEM to rapidly design and bring to volume an RIVA128ZX-based product. This TMP includes: * CD-ROM - RIVA128ZX Datasheet and Application Notes - OrCADTM schematic capture and PADSTM layout design information - Quick Start install/user guide/release notes - BIOS Modification program, BIOS binaries, utilities and BIOS Modification Guide documentation - Bring-up and OEM Production Diagnostics - Software and Utilities * OS drivers and files - Windows 3.11 - Windows 95 Direct X/3D - Windows NT 3.5 - Windows NT 4.0 * Content developer and WWW information * Partner solutions * Access to our password-protected web site for upgrade files and release notes.
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RIVA128ZX
4
128-BIT 3D MULTIMEDIA ACCELERATOR
ACCELERATED GRAPHICS PORT (AGP) INTERFACE
The Accelerated Graphics Port (AGP) is a high performance, component level interconnect targeted at 3D graphical display applications and based on performance enhancements to the PCI local bus. Figure 1. System block diagram showing relationship between AGP and PCI buses
CPU
RIVA128ZX
AGP
AGP chipset
System memory
PCI I/O I/O I/O
Background to AGP Although 3D graphics acceleration is becoming a standard feature of multimedia PC platforms, 3D rendering generally has a voracious appetite for memory bandwidth. Consequently there is upward pressure on the PC's memory requirement leading to higher bill of material costs. These trends will increase, requiring high speed access to larger amounts of memory. The primary motivation for AGP therefore was to contain these costs whilst enabling performance improvements. By providing significant bandwidth improvement between the graphics accelerator and system memory, some of the 3D rendering data structures can be shifted into main memory, thus relieving the pressure to increase the cost of the local graphics memory. Texture data are the first structures targeted for shifting to system memory for four reasons: 1 Textures are generally read only, and therefore do not have special access ordering or coherency problems. 2 Shifting textures balances the bandwidth load between system memory and local graphics memory, since a well cached host processor has much lower memory bandwidth requirements than a 3D rendering engine. Texture access comprises perhaps the largest single component of rendering memory bandwidth (compared with rendering, display and Z buffers), so avoiding loading or caching textures in graphics
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local memory saves not only this component of local memory bandwidth, but also the bandwidth necessary to load the texture store in the first place. Furthermore, this data must pass through main memory anyway as it is loaded from a mass store device. 3 Texture size is dependent upon application quality rather than on display resolution, and therefore subject to the greatest pressure for growth. 4 Texture data is not persistent; it resides in memory only for the duration of the application, so any system memory spent on texture storage can be returned to the free memory heap when the application finishes (unlike display buffers which remain in use). Other data structures can be moved to main memory but the biggest gain results from moving texture data. Relationship of AGP to PCI AGP is a superset of the 66MHz PCI Specification (Revision 2.1) with performance enhancements optimized for high performance 3D graphics applications. The PCI Specification is unmodified by AGP and `reserved' PCI fields, encodings and pins, etc. are not used. AGP does not replace the need for the PCI bus in the system and the two are physically, logically, and electrically independent. As shown in Figure 1
128-BIT 3D MULTIMEDIA ACCELERATOR
the AGP bridge chip and RIVA128ZX are the only devices on the AGP bus - all other I/O devices remain on the PCI bus. The add-in slot defined for AGP uses a new connector body (for electrical signaling reasons) which is not compatible with the PCI connector; PCI and AGP boards are not mechanically interchangeable. AGP accesses differ from PCI in that they are pipelined. This compares with serialized PCI 4.1 RIVA128ZX AGP INTERFACE
RIVA128ZX
transactions, where the address, wait and data phases need to complete before the next transaction starts. AGP transactions can only access system memory - not other PCI devices or CPU. Bus mastering accesses can be either PCI or AGPstyle. Full details of AGP are given in the Accelerated Graphics Port Interface Specification [3] published by Intel Corporation.
The RIVA128ZX glueless interface to AGP 1.0 is shown in Figure 2. Figure 2. AGP interface pin connections
PCIAD[31:0]
32
PCICBE[3:0]#
4
AGPST[2:0]#
3
AGPRBF# AGPPIPE# PCIDEVSEL# AGP bus PCIIRDY# PCITRDY# PCISTOP# PCIIDSEL PCIPAR PCIREQ# PCIGNT# PCICLK PCIRST# PCIINTA# RIVA128ZX
4.2
AGP BUS TRANSACTIONS
PCI transactions on the AGP bus PCI transactions can be interleaved with AGP transactions including between pipelined AGP data transfers. A basic PCI transaction on the AGP interface is shown in Figure 3. If the PCI target is a non AGP compliant master, it will not see AGPST[2:0] and the transaction appears to be on a PCI bus. For AGP aware bus masters, AGPST[2:0] indicate that permission to use the interface has been granted to initiate a request and not to move AGP data.
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AGP bus commands supported The following AGP bus commands are supported by the RIVA128ZX: - Read - Read (hi-priority)
RIVA128ZX
Figure 3. Basic PCI transaction on AGP 1
PCICLK PCIFRAME# PCIAD[31:0] PCICBE[3:0]# PCIIRDY# PCITRDY# PCIDEVSEL# PCIREQ# PCIGNT# AGPST[2:0]
128-BIT 3D MULTIMEDIA ACCELERATOR
2
3
4
5
6
address bus cmd
data_pci BE[3:0]#
xxx
111
111
xxx
xxx
xxx
An example of a PCI transaction occurring between an AGP command cycle and return of data is shown in Figure 4. This shows the smallest number of cycles during which an AGP request can be enqueued, a PCI transaction performed and AGP read data returned. Figure 4. PCI transaction occurring between AGP request and data 1
PCICLK AGPPIPE# PCIFRAME# PCIAD[31:0] PCICBE# PCIIRDY# PCITRDY# PCIDEVSEL# PCIAGPRBF# PCIREQ# PCIGNT# AGPST[2:0] 111 111 xxx 111 111 xxx xxx 00x xxx xxx A9 C9 address pci_cmd data BE D7 0000 +1 000
2
3
4
5
6
7
8
9
10
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 5. Basic AGP pipeline concept
RIVA128ZX
Bus Idle
Pipelined data transfer
Data-1
Data-2
Data-3
Intervene cycles
A1
A2
A3
A
Data
Pipelined AGP requests
PCI transaction
Pipeline operation Memory access pipelining provides the main performance enhancement of AGP over PCI. AGP pipelined bus transactions share most of the PCI signal set, and are interleaved with PCI transactions on the bus. The RIVA128ZX supports AGP pipelined reads with a 4-deep queue of outstanding read requests. Pipelined reads are primarily used by the RIVA128ZX for cache filling, the cache size being optimized for AGP bursts. Depending on the AGP bridge, a bandwidth of up to 248MByte/s is achievable for 128-byte pipelined reads. This compares with around 100MByte/s for 128-byte 33MHz PCI reads. Another feature of AGP is that for smaller sized reads the bandwidth is not significantly reduced. Whereas 16-byte reads on PCI transfer at around 33MByte/s, on AGP around 175MByte/s is achievable. The RIVA128ZX actually requests reads greater than 64 bytes in multiples of 32-byte transactions. The pipe depth can be maintained by the AGP bus master (RIVA128ZX) intervening in a pipelined transfer to insert new requests between data replies. This bus sequencing is illustrated in Figure 5. When the bus is in an idle condition, the pipe can be started by inserting one or more AGP access requests consecutively. Once the data reply to those accesses starts, that stream can be broken (or intervened) by the bus master (RIVA128ZX) inserting one or more additional AGP access requests or inserting a PCI transaction. This intervention is accomplished with the bus ownership signals, PCIREQ# and PCIGNT#.
The RIVA128ZX implements both high and low priority reads depending of the status of the rendering engine. If the pipeline is likely to stall due to system memory read latency, a high priority read request is posted. Address Transactions The RIVA128ZX requests permission from the bridge to use PCIAD[31:0] to initiate either an AGP request or a PCI transaction by asserting PCIREQ#. The arbiter grants permission by asserting PCIGNT# with AGPST[2:0] equal to "111" (referred to as START). When the RIVA128ZX receives START it must start the bus operation within two clocks of the bus becoming available. For example, when the bus is in an idle condition when START is received, the RIVA128ZX must initiate the bus transaction on the next clock and the one following. Figure 6 shows a single address being enqueued by the RIVA128ZX. Sometime before clock 1, the RIVA128ZX asserts PCIREQ# to gain permission to use PCIAD[31:0]. The arbiter grants permission by indicating START on clock 2. A new request (address, command and length) are enqueued on each clock in which AGPPIPE# is asserted. The address of the request to be enqueued is presented on PCIAD[31:3], the length on PCIAD[2:0] and the command on PCICBE[3:0]#. In Figure 6 only a single address is enqueued since AGPPIPE# is just asserted for a single clock. The RIVA128ZX indicates that the current address is the last it intends to enqueue when AGPPIPE# is asserted and PCIREQ# is deasserted (occurring on clock 3). Once the arbiter detects the assertion of AGPPIPE# or PCIFRAME# it deasserts PCIGNT# on clock 4.
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RIVA128ZX
Figure 6. Single address - no delay by master 1
PCICLK AGPPIPE# PCIAD[31:0] PCICBE[3:0]# PCIREQ# PCIGNT# AGPST[2:0] xxx 111 111 xxx A1 C1
128-BIT 3D MULTIMEDIA ACCELERATOR
2
3
4
5
6
7
8
xxx
xxx
xxx
xxx
Figure 7 shows the RIVA128ZX enqueuing 4 requests, where the first request is delayed by the maximum 2 cycles allowed. START is indicated on clock 2, but the RIVA128ZX does not assert AGPPIPE# until clock 4. Note that PCIREQ# remains asserted on clock 6 to indicate that the current request is not the last one. When PCIREQ# is deasserted on clock 7 with AGPPIPE# still asserted this indicates that the current address is the last one to be enqueued during this transaction. AGPPIPE# must be deasserted on the next clock when PCIREQ# is sampled as deasserted. If the RIVA128ZX wants to enqueue more requests during this bus operation, it continues asserting AGPPIPE# until all of its requests are enqueued or until it has filled all the available request slots provided by the target. Figure 7. Multiple addresses enqueued, maximum delay by RIVA128ZX 1
PCICLK AGPPIPE# PCIAD[31:0] PCICBE# PCIREQ# PCIGNT# AGPST[2:0] xxx 111 111 111 xxx xxx xxx xxx A1 C1 A2 C2 A3 C3 A4 C4
2
3
4
5
6
7
2X Data Transfers 2X data transfers are similar to 1X transfers except that an entire 8 bytes are transferred during a single PCICLK period. This requires that two 4 byte pieces of data are transferred across PCIAD[31:0] for each CLK period. A read data transfer is described followed by a write transfer.
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 8. 2X Read data, no delay 1
PCICLK PCIAD[31:0] AGPADSTBx AGPRBF# PCITRDY# PCIREQ# PCIGNT# AGPST[2:0] xxx 00x xxx xxx xxx xxx xxx R1 +1 +2 +3 +4 +5 +6 +7
RIVA128ZX
2
3
4
5
6
7
Figure 8 shows 32 bytes being transferred during 4 clocks (compared with 16 bytes in AGP 1x mode). The control signals are identical. The AGPAD_STBx signal has been added when data is transferred at 8 bytes per PCICLK period. AGPAD_STBx represents AGPAD_STB0 and AGPAD_STB1 and are used by the 2X interface logic to indicate when valid data is present on the AD bus. The control logic (PCITRDY# in this case) indicates when data can be used by the target. Figure 9. 2X Back to back read data, no delay 1
PCICLK PCIAD[31:0] AGPADSTBx AGPRBF# PCITRDY# PCIGNT# AGPST[2:0] xx 000 001 000 001 000 001 000 001 xx L6 +1 H4 +1 +L7 +1 H5 +1 L8 +1 H6 +1 L9 +1
2
3
4
5
6
7
8
9
Figure 9 shows back to back 8 byte read transactions. AGPST[2:0] are shown toggling between "000"and "001" to illustrate that they are actually changing. However, they are not required to change between high and low priority to do back to back transactions. In this diagram, PCITRDY# is asserted on each clock since a new transaction starts on each clock.
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RIVA128ZX
Figure 10. 2X Basic write no delay 1
PCICLK PCIAD[31:0] PCICBE# AGPADSTBx PCIIRDY# PCITRDY# PCIREQ# PCIGNT# AGPST[2:0] xx xxx xxx 01x
128-BIT 3D MULTIMEDIA ACCELERATOR
2
3
4
5
6
7
8
9
W1 +1 +2 +3 +4 +5 +6 +7 BE BE BE BE BE BE BE BE
xxx
xxx
xxx
xxx
xxx
Figure 10 is a basic write transaction that transfers data at the 2X rate. There is no difference in the control signals from AGP 1x mode - only more data is moved. The normal control signals determine when data is valid. Figure 11. QuadWord writes back to back - no delays 1
PCICLK PCIAD[31:0] PCICBE# AGPADSTBx PCIIRDY# PCITRDY# PCIGNT# AGPST[2:0] xx 01x 01x 01x 01x xxx
W3 +1 W4 BE +1 W5 BE BE +1 BE W6 BE +1 BE W7 BE +1 BE W8 BE +1 BE
2
3
4
5
6
7
8
9
BE BE
01x
01x
xxx
x
Figure 11 illustrates multiple 8 byte write operations compared with the single transfer shown in Figure 10. When the transactions are short, the arbiter is required to give grants on every clock or the AD bus will not be totally utilized. In this example a new write is started on each rising clock edge except clock 7, because the arbiter deasserted PCIGNT# on clock 6. Since a new transaction is started on each CLK, PCIIRDY# is only deasserted on clock 7.
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128-BIT 3D MULTIMEDIA ACCELERATOR
AGP timing specification Figure 12. AGP clock specification
RIVA128ZX
0.6VDD 0.5VDD
tCYC
tHIGH
tLOW
2V p-to-p (minimum)
PCICLK 0.4VDD
0.3VDD 0.2VDD
Table 1. AGP clock timing parameters
Symbol tCYC tHIGH tLOW PCICLK period PCICLK high time PCICLK low time PCICLK slew rate
NOTES 1 This rise and fall time is measured across the minimum peak-to-peak range as shown in Figure 12.
Parameter
Min. 15 6 6 1.5
Max. 30
Unit ns ns ns
Notes
4
V/ns
1
Figure 13. AGP timing diagram
tVAL AGPCLK Output delay tOFF tON Tri-state output data1
tVAL
data2
Input
tH tSU data1
data2
Table 2. AGP timing parameters
Symbol tVAL tON tOFF tSU tH Parameter AGPCLK to signal valid delay (data and control signals) Float to active delay Active to float delay Input set up time to AGPCLK (data and control signals) Input hold time from AGPCLK 7 0 Min. 2 2 28 Max. 11 Unit ns ns ns ns ns Notes
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 14. AGP timing diagram (2X data transfer mode)
AGPCLK Output data Data1 tDVA tDVB tTSF tTSR Output strobe Input data Data1 tDH tDSU tRSH Input strobe tDSU Data2 tDH tRSSU Data3 Data4 tDVB Data2 Data3 Data4
tDVA
Table 3. AGP timing parameters (2X data transfer mode)
Symbol tTSF tTSR tDVB tDVA tRSSU tRSH tDSU tDH Parameter AGPCLK to transmit strobe falling edge AGPCLK to transmit strobe rising edge Output data valid before strobe Output data valid after strobe Receiver strobe setup time to AGPCLK Receiver strobe hold time from AGPCLK Input data to strobe setup time Input data to strobe hold time 1.7 1.7 6 1 1 1 Min. 2 Max. 12 20 Unit ns ns ns ns ns ns ns ns Notes
Figure 15. AGP Strobe/Data turnaround timing diagram (2X data transfer mode)
AGPCLK tOFFD PCIAD[31:0] tOFFS AGPADSTBx tONS tOND
Table 4. AGP Strobe/Data turnaround timing parameters (2X data transfer mode)
Symbol tOND tOFFD tONS tOS Parameter Float to active delay Active to float delay Strobe active to strobe falling edge setup Strobe rising edge to strobe float delay Min. -1 1 6 6 Max. 9 12 10 10 Unit ns ns ns ns Notes
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128-BIT 3D MULTIMEDIA ACCELERATOR
5 5.1 PCI 2.1 LOCAL BUS INTERFACE RIVA128ZX PCI INTERFACE
RIVA128ZX
The RIVA128ZX supports a glueless interface to PCI 2.1 with both master and slave capabilities. The host interface is fully compliant with the 32-bit PCI 2.1 specification. The Multimedia Accelerator supports PCI bus operation up to 33MHz with zero-wait state capability and full bus mastering capability handling burst reads and burst writes. Figure 16. PCI interface pin connections
PCIAD[31:0]
32
PCICBE[3:0]#
4
PCIFRAME# PCIDEVSEL# PCIIRDY# PCI bus PCITRDY# PCISTOP# PCIIDSEL PCIPAR PCIREQ# PCIGNT# PCICLK PCIRST# PCIINTA# RIVA128ZX
Table 5. PCI bus commands supported by the RIVA128ZX
Bus master Memory read and write Memory read line Memory read multiple Bus slave Memory read and write I/O read and write Configuration read and write Memory read line Memory read multiple Memory write invalidate
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RIVA128ZX
5.2 PCI TIMING SPECIFICATION
128-BIT 3D MULTIMEDIA ACCELERATOR
The timing specification of the PCI interface takes the form of generic setup, hold and delay times of transitions to and from the rising edge of PCICLK as shown in Figure 17. Figure 17. PCI timing parameters
PCICLK tVAL Output timing parameters Output delay tON tOFF Tri-state output
PCICLK Input timing parameters tSU Input tH
Table 6. PCI timing parameters
Symbol tVAL tVAL tON tOFF tSU tSU(PTP) tSU(PTP) tH
NOTE 1 PCIREQ# and PCIGNT# are point to point signals and have different valid delay and input setup times than bussed signals. All other signals are bussed.
(PTP)
Parameter PCICLK to signal valid delay (bussed signals) PCICLK to signal valid delay (point to point) Float to active delay Active to float delay Input set up time to PCICLK (bussed signals) Input set up time to PCICLK (PCIGNT#) Input set up time to PCICLK (PCIREQ#) Input hold time from PCICLK
Min. 2 2 2
Max. 11 12
Unit ns ns ns
Notes 1 1
28 7 10 12 0
ns ns ns ns ns 1 1
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 18. PCI Target write - Slave Write (single 32-bit with 1-cycle DEVSEL# response)
PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# (med) address bus cmd data BE[3:0]#
RIVA128ZX
Figure 19. PCI Target write - Slave Write (multiple 32-bit with zero wait state DEVSEL# response)
PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd data0 BE[3:0]# data1 BE[3:0]# data2 BE[3:0]#
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 20. PCI Target read - Slave Read (1-cycle single word read)
PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# data0
Figure 21. PCI Target read - Slave Read (slow single word read)
PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# data0
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 22. PCI Master write - multiple word
RIVA128ZX
PCICLK PCIREQ# PCIGNT# PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd data0 BE[3:0]# data1 BE[3:0]# data2 BE[3:0]# data3 BE[3:0]#
Figure 23. PCI Master read - multiple word
PCICLK PCIREQ# PCIGNT# PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# data0 BE[3:0]# data1
Note: The RIVA128ZX does not generate fast back to back cycles as a bus master
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 24. PCI Target configuration cycle - Slave Configuration Write
PCICLK AD[31:0] PCICBE[3:0]# PCIFRAME# PCIIDSEL PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd data0 BE[3:0]#
(med)
Figure 25. PCI Target configuration cycle - Slave Configuration Read
PCICLK PCIAD[31:0] PCICBE[3:0]# PCIFRAME# PCIIDSEL PCIIRDY# PCITRDY# PCIDEVSEL# address bus cmd BE[3:0]# config_data
(med)
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 26. PCI basic arbitration cycle
RIVA128ZX
PCICLK PCIREQ#_a PCIREQ#_b PCIGNT#_a PCIGNT#_b PCIFRAME# PCIAD[31:0] address access A data address data
access B
Figure 27. Target initiated termination
PCICLK
1 2 3 4 1 2 3 4
PCIFRAME# PCIIRDY# PCITRDY# PCISTOP# PCIDEVSEL# Disconnect - A Disconnect - B
PCICLK PCIFRAME# PCIIRDY# PCITRDY# PCIPCISTOP# PCIDEVSEL#
1
2
3
4
5
1
2
3
4
Disconnect - C / Retry
Target - Abort
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RIVA128ZX
6 FRAMEBUFFER INTERFACE
128-BIT 3D MULTIMEDIA ACCELERATOR
The RIVA128ZX framebuffer interface supports SDRAM and SGRAM memory. Using SDRAM it can be configured with an 8MByte 64-bit data bus. With SGRAM it can be configured with a 2 or 4MByte 64-bit data bus or a 4 or 8MByte 128-bit data bus. The memory configurations supported by RIVA128ZX are shown in Table 7. All of the framebuffer signalling environment is 3.3V. Table 7. RIVA128ZX memory configurations
8Mbit 2 internal bank SGRAM 2MByte 4MByte 8MByte 2 devices 64-bit 4 devices 128-bit 2 banks of 4 devices 128-bit 16Mbit 2 internal bank SGRAM N/A 2 devices 64-bit 4 devices 128-bit 16Mbit 4 internal bank SGRAM N/A 2 devices 64-bit 4 devices 128-bit 16Mbit 1M x 16 SDRAM N/A N/A 4 devices 64-bit
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128-BIT 3D MULTIMEDIA ACCELERATOR
6.1 SDRAM INTERFACE
RIVA128ZX
Two extra address lines are required to support 8MByte SDRAM compared with those needed for 4MByte SGRAM on RIVA 128. These are the A10 signal which was defined on the RIVA 128 pinout for future expansion and the SDRAM's internal bank select address bit (BA signal). To provide this extra signal the RIVA128ZX FBCS[1]# pin is internally redefined to be the SDRAM BA/A11 signal. Since the RIVA128ZX supports a maximum addressable memory of 8MBytes, SDRAM support is only allowed with a 64-bit data bus. Figure 28 shows an example SDRAM memory configuration for RIVA128ZX. Note this figure attempts to scramble the bytes and data bits within bytes to simplify board layout, but this will depend on how the board components are placed in the layout. Figure 28. 8MByte SDRAM configuration using 16Mbit devices
FBCS[1]# FBA[10:0] FBRAS# FBCAS# FBWE# FBCKE#
WE CKE CAS RAS A[10:0] BA WE CKE CAS RAS A[10:0] BA
FBDQM[3]# FBDQM[0]# FBCS[0]# FBCLK0
DQML DQMH CS CLK
FBD[31:24] FBD[7:0]
FBDQM[1]# FBDQM[2]# FBCS[0]# FBCLK0
DQML DQMH CS CLK
FBD[15:8] FBD[23:16]
1Mx16 SDRAM
1Mx16 SDRAM
FBDQM[5]# FBDQM[6]# FBCS[0]# FBCLK1 FBD[127:0]
DQML DQMH CS CLK
FBCS[1]# FBA[10:0] FBRAS# FBCAS# FBWE# FBCKE#
WE CKE CAS
1Mx16 SDRAM
RAS
A[10:0]
BA
WE CKE
CAS
RAS
A[10:0]
BA
FBD[47:40] FBD[55:48]
FBDQM[4]# FBDQM[7]# FBCS[0]# FBCLK1
DQML DQMH CS CLK
FBD[32:39] FBD[56:63]
1Mx16 SDRAM
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RIVA128ZX
6.2 SGRAM INTERFACE
128-BIT 3D MULTIMEDIA ACCELERATOR
Signal changes between RIVA 128 and RIVA128ZX The extra address signal (FBA[10]) required to address 16Mbit SGRAM devices was defined on RIVA 128 and was connected to pin 30 of the SGRAM in the RIVA 128 Reference Design schematics. This pin is a N/C on 8Mbit memory devices and it was also N/C on RIVA 128. For 8MByte designs using 8Mbit devices; FBCS0# drives the chip selects for the first external bank of memory and FBCS1# drives the second external bank. The ROM BIOS implements code which automatically detects the configuration and memory type. If a mixture of 4-internal bank and 2-internal bank 16Mbit devices are used (e.g. 2 soldered down and 2 added by an end user as an SO-DIMM) then RIVA128ZX will program those devices and operate itself as 2-internal bank. There is no support for mixed 16Mbit and 8Mbit memories (i.e. there is no 6MByte mode) nor is there support for 16MByte using eight 16Mbit devices. The upgrade path from two devices to four devices has also been changed to better accommodate board layout for SO-DIMMs. As shown in Figure 29, the first two memories installed are on the left side of the chip and the upgrade is on the right hand side. This is different to RIVA 128 which populated the top two chips first and then populated the lower (far left and far right) memories as the upgrade. Both forms of 64-bit bus are supported in RIVA128ZX and the data paths populated are determined by the BIOS during its boot memory detection sequence. Figure 29. Upgrade from 64-bit 4MByte to 128-bit 8MByte SGRAM via SO-DIMM
First two memories installed Bank 2 512K x32
Bank 0 512K x32
Bank 1 512K x32
Upgrade to 8MByte via SO-DIMM Bank 3 512K x32
FBD[31:0] FBD[95:64] RIVA128ZX
FBD[63:32] FBD[127:96]
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 30. 4 MByte SGRAM configurations using 16Mbit devices
FBA[10:0] FBRAS# FBCAS# FBWE# FBCKE#
RIVA128ZX
a. RIVA 128 layout compatible
FBDQM[0]# FBDQM[1]# FBDQM[2]# FBDQM[3]# FBCS[0]# FBCLK0 FBD[127:0] Bank 0 512Kx32 SGRAM FBD[31:0]
FBDQM[4]# FBDQM[5]# FBDQM[6]# FBDQM[7]# FBCS[0]# FBCLK1 Bank 1 512Kx32 SGRAM FBD[63:32]
FBA[10:0] FBRAS# FBCAS# FBWE# FBCKE#
b. Compatible with RIVA128ZX layout implementing SO-DIMM upgrade to 8Mbytes
FBDQM[0]# FBDQM[1]# FBDQM[2]# FBDQM[3]# FBCS[0]# FBCLK0 FBD[127:0] Bank 0 512Kx32 SGRAM FBD[31:0]
FBDQM[8]# FBDQM[9]# FBDQM[10]# FBDQM[11]# FBCS[1]# FBCLK0 Bank 2 512Kx32 SGRAM FBD[95:64]
NOTE 1 The 64-bit bus data paths populated by RIVA128ZX are determined by the BIOS during its boot memory detection sequence.
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 31. 8MByte SGRAM configuration using 16Mbit devices
FBA[10:0] FBRAS# FBCAS# FBWE# FBCKE# FBDQM[8]# FBDQM[9]# Bank 0 512Kx32 SGRAM FBD[31:0] FBDQM[10]# FBDQM[11]# FBCS[1]# FBCLK0 Bank 2 512Kx32 SGRAM FBD[95:64]
FBDQM[0]# FBDQM[1]# FBDQM[2]# FBDQM[3]# FBCS[0]# FBCLK0
FBA[10:0] FBRAS# FBCAS# FBWE# FBCKE# FBDQM[12]# FBDQM[13]# Bank 1 512Kx32 SGRAM FBD[63:32] FBDQM[14]# FBDQM[15]# FBCS[1]# FBCLK1 Bank 3 512Kx32 SGRAM FBD[127:96]
FBDQM[4]# FBDQM[5]# FBDQM[6]# FBDQM[7]# FBCS[0]# FBCLK1
FBD[127:0]
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128-BIT 3D MULTIMEDIA ACCELERATOR
6.3 SDRAM/SGRAM ACCESSES AND COMMANDS
RIVA128ZX
Read and write accesses to SDRAM/SGRAM are burst oriented. SDRAM/SGRAM commands supported by the RIVA128ZX are shown in Table 9. Initialization of the memory devices is performed in the standard SDRAM/SGRAM manner. Access sequences begin with an Active command followed by a Read or Write command. The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. The RIVA128ZX always uses a burst length of one and can launch a new read or write on every cycle. SDRAM/SGRAM has a fully synchronous interface with all signals registered on the positive edge of FBCLKx. Multiple clock outputs allow reductions in signal loading and more accuracy in data sampling at high frequency. The clock signals can be interspersed as shown in Figure 30, page 33 for optimal loading with either 4 or 8MBytes. The I/O timings relative to FBCLKx are shown in Figure 32, page 37. Table 8. Truth table of supported SDRAM commands
Command1 Command inhibit (NOP) No operation (NOP) Active (select bank and activate row) Read (select bank and column and start read burst) Write (select bank and column and start write burst) Precharge (deactivate row in bank or banks) Load mode register FBCS0# FBRAS# FBCAS# FBWE# H L L L x H L H x H H L x H H H FBDQM x x x x FBCS[1]#, FBA[10:0] x x FBCS[1]#=bank FBA[10:0]=row FBCS[1]#=bank FBA[10]=0 FBA[7:0]=col FBD[63:0] Notes x x x x
L
H
L
L
x
FBCS[1]#=bank valid data FBA[10]=0 FBA[7:0]=col FBA[10]=code FBCS[1]#, FBA[10:0] = opcode active high-Z 2 2 x 3
L L
L L
H L
L L
x x
Write enable/output enable Write inhibit/output High-Z
NOTES 1 2 3
-
-
-
-
L H
FBCKE is high and DSF is low for all supported commands. Activates or deactivates FBD[63:0] during writes (zero clock delay) and reads (two-clock delay). For FBA10 low, FBCS[1]# determines which bank is precharged; for FBA10 high, all banks are precharged irrespective of the state of FBCS[1]#.
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Table 9. Truth table of supported SGRAM commands
Command1 Command inhibit (NOP) No operation (NOP) Active (select bank and activate row) Read (select bank and column and start read burst) Write (select bank and column and start write burst) Precharge (deactivate row in bank or banks) Load mode register Write enable/output enable Write inhibit/output High-Z
NOTES 1 2 3 FBCKE is high and DSF is low for all supported commands. Activates or deactivates FBD[127:0] during writes (zero clock delay) and reads (two-clock delay). For FBA9 low, FBA10 determines which bank is precharged; for FBA9 high, all banks are precharged irrespective of the state of FBA10.
FBCS0#, FBRAS# FBCAS# FBWE# FBCS1# H L L L x H L H x H H L x H H H
FBDQM x x x x
FBA[10:0] x x FBA[10]=bank FBA[9:0]=row FBA[10]=bank FBA[9]=0 FBA[7:0]=col FBA[10]=bank FBA[9]=0 FBA[7:0]=col FBA[10]=code FBA[10:0] = opcode -
FBD[127:0] Notes x x x x
L
H
L
L
x
valid data
L L -
L L -
H L -
L L -
x x L H
x
3
active high-Z
2 2
SDRAM/SGRAM Initialization SDRAM/SGRAMs must be powered-up and initialized in a predefined manner. The first SDRAM/SGRAM command is registered on the first clock edge following PCIRST# inactive. All internal SDRAM/SGRAM banks are precharged to bring the device(s) into the "all bank idle" state. The SDRAM/SGRAM mode registers are then programmed and loaded to bring them into a defined state before performing any operational command. SDRAM/SGRAM Mode register The Mode register defines the mode of operation of the SDRAM/SGRAM. This includes burst length, burst type, read latency and SDRAM/SGRAM operating mode. The Mode register is programmed via the Load Mode register and retains its state until reprogrammed or power-down. Mode register bits M[2:0] specify the burst length; for the RIVA128ZX SDRAM/SGRAM interface these bits are set to zero, selecting a burst length of one. In this case FBA[7:0] select the unique column to be accessed and Mode register bit M[3] is ignored. Mode register bits M[6:4] specify the read latency; for the RIVA128ZX SDRAM/SGRAM interface these bits are set to either 2 or 3, selecting a burst length of 2 or 3 respectively.
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128-BIT 3D MULTIMEDIA ACCELERATOR
6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS
RIVA128ZX
Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of memory to give reduced clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and FBCLKFB. It is recommended that long traces are used without tunable components. If the layout includes provision for expansion to 8MBytes, the clock path to the 4MByte parts should be at the end of the trace, and the clock path to the 8MByte expansion located between the RIVA128ZX and the 4MByte parts as shown in Figure 32. FBCLK2 and FBCLKFB should be shorted together as close to the package as possible. Figure 32. Recommended memory clock layout
Expansion to 8MBytes
FBCLK2 FBCLKFB RIVA128ZX FBCLK0
Bank 1
512K x32
Bank 0
512K x32
t t FBCLK1 512K x32 512K x32
6.5
FRAMEBUFFER INTERFACE TIMING SPECIFICATION
Figure 33. SDRAM/SGRAM I/O timing diagram
tCK FBCLKx tCH tAS, tDS tAH, tDH tAC FBD[63:0] tLZ tOH tCL
FBA[10:0], FBD[63:0]
Table 10. SDRAM/SGRAM I/O timing parameters
Symbol Parameter -10 Min. -12 12 4.5 4.5 4 1 4 -10 Max. -12 ns ns ns ns ns ns Unit Notes
tCK tCH tCL tAS tAH tDS
CLK period CLK high time CLK low time Address setup time Address hold time Write data setup time
10 3.5 3.5 3 1 3
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RIVA128ZX
Symbol Parameter -10 Min.
128-BIT 3D MULTIMEDIA ACCELERATOR
Max. -12 1 3 9 0 -10 -12 ns ns ns ns Unit Notes
tDH tOH tAC tLZ
Write data hold time Read data hold time Read data access time Data out low impedance time
1 3 9 0
Figure 34. SDRAM/SGRAM random read accesses within a page, read latency of two1
FBCLKx Command FBA[10:0] FBD[63:0] read read read read nop nop
bank, col n bank, col a bank, col x bank, col m data n data a data x data m
NOTE 1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. DQMs are all active (LOW).
Figure 35. SDRAM/SGRAM random read accesses within a page, read latency of three1
FBCLKx Command FBA[10:0] FBD[63:0] read read read read nop nop nop
bank, col n bank, col a bank, col x bank, col m
data n
data a
data x
data m
NOTE 1 Covers either successive reads to the active row in a given bank, or to the active rows in different banks. FBDQM is all active (LOW).
Figure 36. SDRAM/SGRAM read to write, read latency of three
FBCLKx TDDQM Command FBA[10:0] read bank, col n nop nop nop write bank, col b
FBD[63:0]
tHZ
read data n
tDS
write data b
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128-BIT 3D MULTIMEDIA ACCELERATOR
Table 11. SDRAM/SGRAM I/O timing parameters
Symbol Parameter Data out high impedance time Write data setup time Min. 4 4 Max. 10 Unit ns ns
RIVA128ZX
Notes
tHZ tDS
Figure 37. SDRAM/SGRAM random write cycles within a page
FBCLKx Command FBA[10:0] FBD[63:0] write bank, col n data n write bank, col a data a write bank, col x data x write bank, col m data m
NOTE 1 Covers either successive writes to the active row in a given bank or to the active rows in different banks. FBDQM is active (low).
Figure 38. SDRAM/SGRAM write to read cycle
FBCLKx Command FBA[10:0] FBD[63:0] write bank, col n write data n nop read bank, col b nop nop nop
write data n
read data b
NOTE 1 A read latency of 2 is shown for illustration
Figure 39. SDRAM/SGRAM read to precharge, read latency of two
tRP
FBCLKx Command FBA[10:0] FBD[63:0]
read precharge nop
nop
active
bank,row
bank, col n bank(s) data n
NOTE 1 FBDQM is active (low)
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 40. SDRAM/SGRAM read to precharge, read latency of three
FBCLKx Command FBA[10:0] FBD[63:0]
read bank, col n
tRP
precharge nop bank(s) data n nop active bank, row
NOTE 1 FBDQM is active (low)
Figure 41. SDRAM/SGRAM Write to Precharge
tRP FBCLKx FBDQM# Command FBA[10:0] FBD[63:0] write bank, col n tWR write data n write data n+1 nop nop precharge bank(s) nop nop active row
Figure 42. SDRAM/SGRAM Active to Read or Write
FBCLKx Command active nop tRCD nop read or write
Table 12. SDRAM/SGRAM timing parameters
Symbol Parameter FBCSx, FBRAS#, FBCAS#, FBWE#, FBDQM setup time FBCSx, FBRAS#, FBCAS#, FBWE#, FBDQM hold time Load Mode register command to command Active to Precharge command period Active to Active command period Active to Read or Write delay Min. 3 1 2 7 10 3 Max. Unit ns ns tCK tCK tCK tCK Notes
tCS tCH tMTC tRAS tRC tRCD
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128-BIT 3D MULTIMEDIA ACCELERATOR
Symbol Parameter Refresh period (1024 cycles) Precharge command period Active bank A to Active bank B command period Transition time Write recovery time 2 4 3 1 Min. Max. 16 Unit ms tCK tCK ns tCK
RIVA128ZX
Notes
tREF tRP tRRD tT tWR
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RIVA128ZX
7 VIDEO PLAYBACK ARCHITECTURE
128-BIT 3D MULTIMEDIA ACCELERATOR
`temporal averaging' being applied based on intraframing. * Linestore: - To support high quality video playback the RIVA128ZX memory controller and video overlay engine supports horizontal and vertical interpolation using a 3x2 multitap interpolating filter with image sharpening. * YUV to RGB conversion: - YUV 4:2:2 format to 24-bit RGB true-color - Chrominance optimization/user control * Color key video composition
The RIVA128ZX video playback architecture is designed to allow playback of CCIR PAL or NTSC video formats with the highest quality while requiring the smallest video surface. The implementation is optimized around the Windows 95 Direct Video and ActiveX APIs, and supports the following features: * Accepts interlaced video fields: - This allows the off-screen video surface to consume less memory since only one field (half of each frame) is stored. Double buffering between fields is done in hardware with Figure 43. Video scaler pipeline
Linestore
YUV
Vertical Interpolation
Filter (Smooth/Sharpen)
Color Space Conversion to 24-bit RGB
Horizontal Interpolation
24-bit RGB Video output
Video windowing, merge with graphics pixel pipeline
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128-BIT 3D MULTIMEDIA ACCELERATOR
7.1 VIDEO SCALER PIPELINE Horizontal stretching
RIVA128ZX
The RIVA128ZX video scaler pipeline performs stretching of video images in any arbitrary factor in both horizontal and vertical directions. The video scaler pipeline consists of the following stages: 1 Vertical stretching 2 Filtering 3 Color space conversion 4 Horizontal stretching Vertical stretching Vertical stretching is performed on pixels prior to color conversion. The video scaler linearly interpolates the pixels in the vertical direction using an internal buffer which stores the previous line of pixel information. Filtering After vertical interpolation, the pixels are horizontally filtered using an edge-enhancement or a smoothing filter. The edge-enhancement filter enhances picture transition information to prevent loss of image clarity following the smoothing filtering stage. The smoothing filter is a low-pass filter that reduces the noise in the source image. Color space conversion The video overlay pipeline logic converts images from YUV 4:2:2 format to 24-bit RGB true-color. The default color conversion coefficients convert from YCrCb to gamma corrected RGB. Saturation controls make sure that the conversion does not exceed the output range. Four control flags in the color converter provides 16 sets of color conversion coefficients to allow adjustment of the hue and saturation. The brightness of each R G B component can also be individually adjusted, similar to the brightness controls of the monitor.
Horizontal stretching is done in 24-bit RGB space after color conversion. Each component is linearly interpolated using a triangle 2-tap filter. Windowing and panning Video images are clipped to a rectangular window by a pair of registers specifying the position and width. By programming the video start address and the video pitch, the video overlay logic also supports a panning window that can zoom into a portion of the source image. Video composition With the color keying feature enabled, a programmable key in the graphics pixel stream allows selection of either the video or the graphics output on a pixel by pixel basis. Color keying allows any arbitrary portions of the video to overlay the graphics. With color keying disabled and video overlay turned on, the video output overlays the graphics in the video window. Interlaced video The video overlay can display both non-interlaced and interlaced video. Traditional video overlay hardware typically drops every other field of an interlaced video stream, resulting in a low frame rate. Some solutions have attempted to overcome the this problem by deinterlacing the fields into a single frame. This however introduces motion artifacts. Fast moving objects appearing in different positions in different fields, when deinterlaced, introduces visible artifacts which look like hair-like lines projecting out of the object.
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RIVA128ZX
Figure 44. Displaying 2 fields with 1:1 ratio
Frame 1 (Top field)
128-BIT 3D MULTIMEDIA ACCELERATOR
Frame 2 (Bottom field)
Line 10 Line 11 Interpolated line (Line 11 & 13) Line 12 Line 13 Interpolated line (Line 10 & 12)
The RIVA128ZX video overlay handles interlaced video by displaying every field, at the original frame rate of the video (50Hz for PAL and 60Hz for NTSC). The video scaling logic upscales, in the vertical direction, the luma components in each field and linearly interpolates successive lines to produce the missing lines of each field. This interpolated scale is applied such that the full frame size of each field is stretched to the desired height.
The video scaler offsets the bottom field image by half a source image line to ensure that both frames when played back align vertically.
The vertical filtering results in a smooth high quality video playback. Also by displaying both fields one after another, any motion artifacts often found in deinterlaced video output are removed, because the pixels in each field are displayed in the order in which the original source was captured.
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128-BIT 3D MULTIMEDIA ACCELERATOR
8 VIDEO PORT
RIVA128ZX
- Local interrupt and pixel stream handling - Hardware buffer management of compressed data, decompressed video pixel data and decompressed audio streams * Supports popular video decoders including the Philips SAA7111A, SAA7112, ITT 3225, and Samsung KS0127. The Video Port initiates transfers of video packets over the internal NV bus to either on or off screen surfaces as defined in the DirectDraw and DirectVideo APIs. * Supports filtered down-scaling or decimation * Allows additional devices to be added
The RIVA128ZX Multimedia Accelerator introduces a multi-function Video Port that has been designed to exploit the bus mastering functionality of the RIVA128ZX. The Video Port is compliant with a simplified ITU-R-656 video format with control of attached video devices performed through the RIVA128ZX serial interface. Video Port support includes: * Windows 95 DirectMPEG API acceleration by providing: - Bus mastered compressed data transfer to attached DVD and MPEG-2 decoders Figure 45. Connections to multiple video modules
SDA SCL RIVA128ZX MPCLK MPAD[7:0] MPFRAME# MPDTACK# MPSTOP#
TV tuner Video decoder S Video
PCI/AGP
VMI 1.4 Media Port Controller (MPC) ITU-R-656 DVD Controller
8.1
VIDEO INTERFACE PORT FEATURES
* * *
* * *
Single 8-bit bus multiplexing among four transfer types: video, VBI, host and compressed data Synchronous 40MHz address/data multiplexed bus Hardware-based round-robin scheduler with predictable performance for all transfer types
Supports multiple video modules and one ribbon cable board on the same bus ITU-R-656 Master Mode Video Port - Simplified ITU-R-656 Video Format -- supports HSYNC, VSYNC, ODD FIELD and EVEN FIELD - VBI data output from video decoder is captured as raw or sliced data
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RIVA128ZX
8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC
128-BIT 3D MULTIMEDIA ACCELERATOR
just the initiation of the read cycle. The Media Port transfers the address of the register to be read during this cycle. After completion of the Read Issue cycle the media port goes back to polling for the next transaction. When it receives a Read Data ready command, it will start the next cycle in the read. CPU Register Read Receive Initiated by the MPC ASIC when it has read data ready to be transferred to the media port. The MPC ASIC waits for the next polling cycle and returns a Read Data Ready status. The media port will transfer the read data on the next Read Receive Cycle. The PCI bus will be held off and retry until the register read is complete. Video Compressed Data DMA Write Initiated by the MPC ASIC with the appropriate Polling Command. The media port manages the Video Compressed data buffer in system memory. Each request for data will return 32 bytes in a single burst. Display Data DMA Read Initiated by the MPC ASIC with the polling command. The MPC ASIC initiates this transfer when it wishes to transfer video data in ITU-R-656 format.
The Media Port transfers data using a Polling Protocol. The Media Port is enabled on the RIVA128ZX by the host system software. The first cycle after being enabled is a Poll Cycle. The MPC ASIC must respond to every poll cycle with valid data during DTACK active. If no transactions are needed, it responds with 00h. The Media Port will continue to Poll until a transaction is requested, or until there is a Host CPU access to an external register. Polling Cycle Media Port initiates a Polling Cycle whenever there is no pending transaction. This gives the MPC ASIC a mechanism to initiate a transaction. The valid Polling commands are listed in the Polling Command table. The priority for the polling requests should be to give the Display Data FIFO highest priority. CPU Register Write Initiated by the Host system software. CPU Register Read Issue Initiated by the Host system software. The read differs from the write in the fact that it must be done in two separate transfers. The Read Issue is Table 13. Media Port Transactions
A0 Cycle 11xx0000 00xx---01xx1111 11xx1111 01xx0001 11xx1000 Poll_Cycle CPUWrite CPURead_Issue CPURead_Receive VCD_DMA_Write Display_Data_Read Transaction
Description Polling Cycle CPU Register Write CPU Register Read Issue CPU Register Read Receive Video Compressed Data DMA Write Display Data DMA Read
Table 14. Polling Cycle Commands
BIT 0 1 3 4 Data 000xxxx1 000xxx1x 000x1xxx 0001xxxx 00000000 NV_PME_VMI_POLL_UNCD NV_PME_VMI_POLL_VIDCD NV_PME_VMI_POLL_INT NV_PME_VMI_POLL_CPURDREC NULL Description Request DMA Read of Display Data Request DMA Write of Video Compressed Data Request for Interrupt Respond to Read Issue - Read Data Ready No Transactions requested
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128-BIT 3D MULTIMEDIA ACCELERATOR
8.3 TIMING DIAGRAMS
RIVA128ZX
Figure 46. Poll cycle
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0
Figure 47. Poll cycle throttled by slave
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0
Figure 48. CPU write cycle
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 A1 D
Figure 49. CPU write cycle throttled by slave
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 A1 D
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 50. CPU read issue cycle - cannot be throttled by slave
MPCLK MPFRAME# MP_AD[7:0] A0 A1/D
Figure 51. CPU read_receive cycle
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0
Figure 52. CPU read_receive cycle - throttled by slave
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0
Figure 53. CD write cycle - terminated by master
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 D1 D2 D3
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128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 54. CD write cycle - terminated by slave in middle of transfer
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 XXX A0 D3 D4
RIVA128ZX
Figure 55. CD write cycle - terminated by slave on byte 31
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D30 XXX A0 D31
Figure 56. CD write cycle - terminated by slave on byte 32, no effect
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D30 D31
Figure 57. UCD read cycle, terminated by master, throttled by slave
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# A0 D0 XXX D1 D2 D3
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 58. UCD read cycle, terminated by slave, throttled by slave
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 XXX D1 D2
Figure 59. UCD read cycle, slave termination after MPFRAME# deasserted, data taken
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 D3
Figure 60. UCD read cycle, slave termination after MPFRAME# deasserted, data not taken
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2 D3
Figure 61. UCD read cycle, slave termination after MPFRAME# deasserted, data taken
MPCLK MPFRAME# MP_AD[7:0] MPDTACK# MPSTOP# A0 D0 D1 D2
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128-BIT 3D MULTIMEDIA ACCELERATOR
8.4 656 MASTER MODE
RIVA128ZX
The 656 Master Mode assumes that VID[7:0] and PIXCLK can be tri-stated when the slave is inactive. If a slave cannot tri-state all its signals, an external tri-state buffer is needed. Video data capture Video Port pixel data is clocked into the port by the external pixel clock and then passed to the RIVA128ZX's video capture FIFO. Pixel data capture is controlled by the ITU-R-656 codes embedded in the data stream; each active line beginning with SAV (start active video) and ending with EAV (end active video). In normal operation, when SAV = x00, capture of video data begins, and when EAV = xx1, capture of video data ends for that line. When VBI (Vertical Blanking Interval) capture is active, these rules are modified.
Table 15 shows the Video Port pin definition when the RIVA128ZX is configured in ITU-R-656 Master Mode. Before entering this mode, RIVA128ZX disables all Video Port devices so that the bus is tristated. The RIVA128ZX will then enable the video 656 master device through the serial bus. In this mode, the video device outputs the video data continuously at the PIXCLK rate. Table 15. 656 master mode pin definition
Normal Mode MPCLK MPAD[7:0] MPFRAME# MPDTACK# MPSTOP# 656 Master Mode PIXCLK VID[7:0] Not used Not used Not used
656 master mode timing specification Figure 62. 656 Master Mode timing diagram
t5
PIXCLK
t3 t4
VID[7:0]
t3 t4 t4
t3
Table 16. ITU-R-656 Master Mode timing parameters
Symbol Parameter VID[7:0] hold from PIXCLK high VID[7:0] setup to PIXCLK high PIXCLK cycle time Min. 0 5 35 Max. Unit ns ns ns Notes
t3 t4 t5
NOTE 1
VACTIVE indicates that valid pixel data is being transmitted across the video port.
Table 17. YUV (YCbCr) byte ordering
1st byte U[7:0] Cb[7:0] 2nd byte Y0[7:0] Y0[7:0] 3rd byte V[7:0] Cr[7:0] 4th byte Y1[7:0] Y1[7:0] 5th (next dword) U[7:0] Cb[7:0] 6th byte Y0[7:0] Y0[7:0] 7th byte V[7:0] Cr[7:0]
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RIVA128ZX
8.5 VBI HANDLING IN THE VIDEO PORT
128-BIT 3D MULTIMEDIA ACCELERATOR
the lines specified and framed by normal ITU-R656 SAV/EAV codes. The RIVA128ZX Video Port capture engine starts capturing data at an SAV code controlled by the device driver, and continues capturing data under control of SAV/EAV codes until a specific EAV code identified by the device driver is sampled. VBI capture is then complete for that field. The number of bytes collected will vary depending on the setup of the KS0127. 8.6 SCALING IN THE VIDEO PORT
RIVA128ZX supports two basic modes for VBI data capture. VBI mode 1 is for use with the Philips SAA7111A digitizer, VBI mode 2 is for use with the Samsung KS0127 digitizer. In VBI mode 1, the region to be captured as VBI data is set up in the SAA7111A via the serial interface, and in the RIVA128ZX under software control. The SAA7111A responds by suppressing generation of SAV and EAV codes for the lines selected, and sending raw sample data to the port. The RIVA128ZX Video Port capture engine starts capturing VBI data at an EAV code in the line last active and continues to capture data without a break until it detects the next SAV code. VBI capture is then complete for that field. In VBI mode 2, the region to be captured as VBI data is set up in a similar manner. The KS0127 responds by enabling VBI data collection only during
The RIVA128ZX Video Port allows any arbitrary scale factor between 1 and 31. For best results the scale factors of 1, 2, 3, 4, 6, 8, 12, 16, and 24 are selected to avoid filtering losses. The Video Port decimates in the y-direction, dropping lines every few lines depending on the vertical scaling factor. The intention is to support filtered downscaling in the attached video decoder.
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128-BIT 3D MULTIMEDIA ACCELERATOR
9 BOOT ROM INTERFACE
RIVA128ZX
BIOS and initialization code for the RIVA128ZX is accessed from a 32KByte ROM. The RIVA128ZX memory bus interface signals FBD[15:0] and FBD[31:24] are used to address and access one of 64KBytes of data respectively. The unique decode to the ROM device is provided by the ROMCS# chip select signal. Figure 63. ROM interface
ROMCS# FBD[15:0]
CS A[15:0] D[7:0] WE OE ROM
RIVA128ZX
FBD[31:24] FBD[17] FBD[16]
ROM interface timing specification Figure 64. ROM interface timing diagram
ROM Read FDB[15:0] tBAS tBRCS ROMCS# OE# (FBD[16]) tBOS tBRV WE# (FBD[17]) tBDS tBDBZ FDB[31:24] data tBDH tBDZ tBOH tBRH address tBAH tBRCA
ROM Write FDB[15:0]
address
tBAS
ROMCS# OE# (FBD[16])
tBRCS
tBAH
tBWL
tBWS WE# (FBD[17])
tBWDS
FDB[31:24] data
tBWDH
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RIVA128ZX
Table 18. ROM interface timing parameters
Symbol tBRCS tBRCA tBRV tBRH tBAS tBAH tBOS tBOH tBWS tBWL tBDBZ tBDS tBDH tBDZ tBWDH tBWDS
NOTE 1 2 3
128-BIT 3D MULTIMEDIA ACCELERATOR
Parameter ROMCS# active pulse width ROMCS# precharge time Read valid to ROMCS# active Read hold from ROMCS# inactive Address setup to ROMCS# active Address hold from ROMCS# inactive OE# low from ROMCS# active OE# low to ROMCS# inactive WE# low from ROMCS# active WE# low time Data bus high-z to ROMCS# active Data setup to ROMCS# inactive Data hold from ROMCS# inactive Data high-z from ROMCS# inactive Write data hold from ROMCS# inactive ROM write data setup to ROMCS# active
Min. 20TMCLK-5 TMCLK-5 TMCLK-5 TMCLK-5 TMCLK-5 TMCLK-5
Max.
Unit ns ns ns ns ns ns ns ns ns ns
Notes
2 3 2 3
TMCLK-5 10 0 TMCLK-5 0.5TMCLK-5 TMCLK-5
ns ns ns ns ns ns
TMCLK is the period of the internal memory clock. This parameter is programmable in the range 0 - 3 MCLK cycles This parameter is programmable in the range 0 - 15 MCLK cycles
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128-BIT 3D MULTIMEDIA ACCELERATOR
10 POWER-ON RESET CONFIGURATION
RIVA128ZX
The RIVA128ZX latches its configuration on the trailing edge of RST# and holds its system bus interface in a high impedance state until this time. To accomplish this, pull-up or pull-down resistors are connected to the FBA[9:0] pins as appropriate. Since there are no internal pull-up or pull-down resistors and the address bus should be floating during reset, a resistor value of up to 47K, but no less than 10K, should be sufficient. The power-on reset configuration seen by the chip may be overwritten. The external FBA[9:0] configuration is stored in latches. An additional writable register, containing all of the configuration bits Power-on reset FBA[9:0] bit assignments 9 AGP Mode 8 7 6 Crystal 5
plus an additional STRAP_OVERWRITE bit (register bit [11]), exists in parallel with the latches to allow the host to overwrite the external value. Writing to address BOOT_0 (0x00101000) writes into this register. The STRAP_OVERWRITE bit controls whether the latches or the parallel writable register are selected. When STRAP_OVERWRITE is set to 0, the latched FBA[9:0] configuration is selected. When set to 1, the chip uses the register value. Reading from address BOOT_0 reads either the configuration latches or the parallel register depending on the STRAP_OVERWRITE setting.
4
3 ACPI Supported
2 RAM Type
1 SubVendor
0 Bus Speed
TV Mode
Host RAM Interface Width
[9]
AGP Mode. This bit selects whether the AGP bus 1X or 2X mode is enabled. 0 = AGP 2X mode enabled 1 = AGP 1X mode enabled TV Mode. These bits select the timing format when TV mode is enabled. 00 = Reserved 01 = NTSC 10 = PAL 11 = TV mode disabled Crystal Frequency. This bit should match the frequency of the crystal or reference clock connected to XTALOUT and XTALIN. 0 = 13.500MHz (used where TV output may be enabled) 1 = 14.31818MHz Host Interface 0 = PCI 1 = AGP RAM Width 0 = 64-bit framebuffer data bus width (the upper 64-bit data bus and byte selects are tri-state) 1 = 128-bit framebuffer data bus width Although a 10K resistor is used to strap the default state of this bit in RIVA 128 and RIVA128ZX reference designs, it is ignored by the video BIOS which auto-detects the memory type and configures the RIVA128ZX appropriately. APCI Supported 0 = ACPI registers not supported. This provides compatibility with the PCI register configuration as implemented by RIVA 128. The RIVA128ZX will be identified by DEVICE_ID_CHIP = 0x18 at PCI Configuration offset 0x0. 1 = ACPI registers supported. Power management registers supported in PCI configuration space. The RIVA128ZX will be identified by DEVICE_ID_CHIP = 0x19 at PCI Configuration offset 0x0.
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[8:7]
[6]
[5]
[4]
[3]
RIVA128ZX
[2]
128-BIT 3D MULTIMEDIA ACCELERATOR
RAM Type 0 = 16Mbit, 2 or 4 internal bank SGRAM or 16Mbit SDRAM. The BIOS should test the memory to determine whether it supports 2 or 4 internal banks. 1 = 8Mbit, 2 internal bank SGRAM. Although a 10K resistor is used to strap the default state of this bit in RIVA 128 and RIVA128ZX reference designs, it is ignored by the video BIOS which auto-detects the memory type and configures the RIVA128ZX appropriately. Sub-Vendor. This bit indicates whether the PCI Subsystem Vendor field is located in the system motherboard BIOS or adapter card VGA BIOS. If the Subsystem Vendor field is located in the system BIOS it must be written by the system BIOS to the PCI configuration space prior to running any PnP code. 0 = System BIOS (Subsystem Vendor ID and Subsystem ID set to 0x0000) 1 = Adapter card VGA BIOS (Subsystem Vendor ID and Subsystem ID read from ROM BIOS at location 0x54 - 0x57) Bus Speed. This bit indicates the value returned in the 66MHz bit in the PCI Configuration registers. 0 = RIVA128ZX PCI interface is 33MHz 1 = RIVA128ZX is 66MHz capable
[1]
[0]
The following example configuration is shown in Figure 65: * Subsystem Vendor ID initialized to 0 and writeable by system BIOS (see Appendix A, page 76) * 8Mbit, 2 internal bank, SGRAM * 128-bit framebuffer interface * AGP 2X mode enabled including 66MHz PCI 2.1 compliant subset * Using 13.5000MHz crystal * TV output mode is NTSC Figure 65. Example motherboard configuration
VDD (3.3V)
FBA[0] FBA[1] FBA[2] FBA[3]
AGP
FBA[4]
RIVA128ZX
FBA[5] FBA[6] FBA[7] FBA[8] FBA[9] FBA[10]
SGRAM array
10K
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128-BIT 3D MULTIMEDIA ACCELERATOR
11 DISPLAY INTERFACE * High quality video overlay
RIVA128ZX
11.1 PALETTE-DAC The Palette-DAC integrated into the RIVA128ZX supports a traditional pixel pipeline with the following enhancements: * Support for 10:10:10, 8:8:8, 5:6:5 and 5:5:5 direct color pixel modes * Support for dynamic gamma correction on a pixel by pixel basis * Support for mixed indexed color and direct color pixels * 256 x 24 LUT for 8-bit indexed modes
- Accepts interlaced video fields allowing a reduction in memory buffering requirements while incorporating temporal averaging - Line buffer for horizontal and vertical interpolation of video streams up to square pixel PAL resolution - 3x2 multitap interpolating filter with image sharpening - Color key in all color pixel modes - High quality YUV to RGB conversion with chrominance control.
11.2 PIXEL MODES SUPPORTED 8-bit indexed color In the 8-bit indexed color each 32-bit word contains four 8-bit indexed color pixels, each comprising bits b[7:0] as shown below.
Pixel formats (FBD[31:0]) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 3 Pixel 2 Pixel 1 8 7 6 5 4 3 2 1 0
Pixel 0
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
NOTE 1 This 32-bit representation can be extended to 64-bit and 128-bit widths by duplicating the 32-bit word in little-endian format.
16-bit direct color modes (5:6:5 direct and 5:5:5 with and without gamma correction) In 5:5:5 color modes bit 15 of each pixel can be enabled to select whether pixel data bypasses the LUT to feed the DACs directly, or indirectly, through the LUT, to allow gamma correction to be applied. If not enabled then the bypass mode will always be selected, and the LUT powered down. The 16-bit modes include a 5:6:5 format which always bypasses the LUT.
Pixel formats (FBD[31:0]) 5:6:5 mode Pixel 1 Pixel 0 6543210 Blue gamma Blue bypass Blue bypass
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 0 0 1
NOTE 1
0 1
Red gamma Red bypass Red bypass
Green gamma Green bypass Green bypass
Blue gamma Blue bypass Blue bypass
0 1
Red gamma Red bypass Red bypass
Green gamma Green bypass Green bypass
This 32-bit representation can be extended to 64-bit and 128-bit widths by duplicating the 32-bit word in little-endian format.
32-bit direct color (8:8:8 with gamma correction or 10:10:10 direct) In 32-bit color mode bit 31 of each pixel selects whether pixel data bypasses the LUT, to feed the DACs directly or indirectly, through the LUT, to allow gamma correction to be applied. In the table below the Red, Green and Blue bypass bits are shown individually as R[9:0], G[9:0], and B[9:0] because, in the bypass
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
mode pixel format, the least significant bits of each color are located separately in the top byte of the pixel. This also permits an 8:8:8 mode without gamma with <1% error if desired.
Use of pixel input pins (FBD[31:0]) Pixel 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 1 XXXXXXX Red gamma Green gamma 8 7 6 5 4 3 2 1 0
Blue gamma
X R1 R0 G1 G0 B1 B0 R9 R8 R7 R6 R5 R4 R3 R2 G9 G8 G7 G6 G5 G4 G3 G2 B9 B8 B7 B6 B5 B4 B3 B2
NOTE This 32-bit representation can be extended to 64-bit and 128-bit widths by duplicating the 32-bit word in little-endian format.
Limitations on line lengths Table 19. Permitted line length multiples
bpp Number of pixels that the line length must be a multiple of 8 4 16 2 32 1
11.3 HARDWARE CURSOR The RIVA128ZX supports a 32x32 15bpp full color hardware cursor as defined by Microsoft Windows. * Full color 5:5:5 format * Pixel complement * Transparency * Pixel inversion The cursor pattern is stored in a 2KByte bitmap located in off-screen framestore. Details of programming the hardware cursor are given in the RIVA128ZX Programming Reference Manual [2]. Registers control cursor enabling/disabling, location of cursor bitmap and cursor display coordinates. The cursor data and it's position should only be changed during frame flyback. The cursor should be disabled when not being used.
Cursor format
15 14 13 12 11 10 9 8 A Red 76 5 43 2 Blue 10
Green
The 5-bit RGB color components are expanded to 10 bits per color before combining with the graphics display data. The expanded 10-bit color is composed of the 5-bit cursor color replicated in the upper and lower 5-bit fields. The cursor pixels are combined such that the cursor will overlay a video window if present. Cursor pixel bit 15 (A) is the replace mode bit. When A=1, the cursor pixel replaces the normal display pixel. If A=0, the expanded 30 bits of the cursor color are XORed with the display pixel to provide the complement of the background color. Cursor pixels can be made transparent (normal display pixel is unmodified) by setting to a value of 0x0000. To invert the bits of the normal display pixel, the cursor pixel should be set to 0x7FFF.
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128-BIT 3D MULTIMEDIA ACCELERATOR
11.4 SERIAL INTERFACE The RIVA128ZX serial interface supports connection to DDC1/2B, DDC2AB and DDC2B+ compliant monitors and to serial interface controlled video decoders and tuners. Supported video decoder chips include Philips SAA7110, SAA7111A, ITT 3225 and Samsung KS0127. For details of address locations and protocols applying to specific parts refer to the appropriate manufacturer's datasheet. The serial interface in RIVA128ZX requires operation under software control to provide emulation of
RIVA128ZX
the interface standard. RIVA128ZX can act as a master for communication with slave devices like those mentioned above. It also acts as a master when interfacing to a DDC1/2 compatible monitor. Although it is not Access.bus compatible, it can communicate with a DDC2AB compatible monitor via the DDC2B+ protocol. (No other Access.bus peripherals can be attached although other serial devices may co-reside on the DDC bus). The RIVA128ZX can clock stretch incoming messages in the event that the software handler is interrupted by another task.
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RIVA128ZX
11.5 ANALOG INTERFACE
128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 66. Recommended circuit (crystal circuit is for designs not supporting TV out)
VDD Local PLLVDD plane C5 L1 Power supply
PLLVDD COMP
DACVDD VDD D4-D6 Monitor 75 cable 75 D1-D3 R2-R4
C3 X1 C4
XTALIN RIVA128ZX XTALOUT VREF RSET RED, GREEN, BLUE
C1 C2
GND C6 R1
These components should be placed as close to the RIVA128ZX outputs as possible
Table 20. Table of parts for recommended circuit (Figure 66)
Part number C1 C2 C3, C4 C5, C6 R1 R2-R4 D1-D6 L1 X1 22F 100nF 10pF 10nF 147 75 1N4148 1H 13.50000MHz 14.31818MHz Value tantalum capacitor surface mount capacitor surface mount capacitor surface mount capacitor 1% resistor 1% resistor protection diodes inductor series resonant crystal (used where TV output may be required) series resonant crystal Description
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128-BIT 3D MULTIMEDIA ACCELERATOR
11.6 TV OUTPUT SUPPORT Reference clock options The RIVA128ZX supports two synthesizer reference clock frequencies; 13.5MHz and 14.31818MHz. The reference clock frequency is determined by a crystal or reference clock connected to the XTALIN and XTALOUT pins. Where TV-out is supported, XTALOUT should be driven by a 13.5MHz reference clock derived from an external NTSC/PAL clock source as illustrated in Figure 67. The clock frequency should match the power-on configuration setting described in Section 10, page 55. PAL/NTSC TV interface The RIVA128ZX supports TV output through an external Analog Devices AD722 PAL/NTSC RGB encoder chip as shown in Figure 67. A MicroClock Figure 67. TV output implementation
220F
RIVA128ZX
MK2715 NTSC/PAL clock chip provides a common source for synchronization of the pixel and subcarrier clocks. In TV output modes the RIVA128ZX XTALOUT pin must be externally driven from the MK2715 reference clock output, with XTALIN tied to GND. The MK2715 requires a number of external components for proper operation. For crystal input a parallel resonant 13.5000MHz crystal is recommended, with a frequency tolerance of 50ppm or better. Capacitors should be connected from X1 and X2 to GND as shown in Figure 67. Alternatively a clock input (e.g. ClockCan) can be connected to X1, leaving X2 disconnected. Further details are given in the MK2715 datasheet [8].
75 75 75
R XTALIN
5V
RIN GIN BIN
75
YOUT
220F
G B
COUT
220F
CVOUT
AD722 TV RGB Encoder
RIVA128ZX
220
VIDHSYNC XTALOUT
HSYNC FIN
330
33
REFOUT
33
4XCLK X1/ICLK
MK2715 NTSC/PAL Clock Source
27pF
27pF
13.50000MHz crystal
X2
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RIVA128ZX
Figure 68. Interface to monitor or television
TV RGB Encoder R Y GC B Y/C
75 75 75
128-BIT 3D MULTIMEDIA ACCELERATOR
PAL/NTSC Television
R RIVA128ZX G B
75 75 75 75 75 75
Monitor
Monitor detection Figure 68 shows the typical connection of a television or computer monitor to the RIVA128ZXs' DAC outputs. The RIVA128ZX expects only one output display device to be connected at a time and does not support simultaneous output to both the monitor and television. During system initialization, the BIOS detects if a monitor is connected by sensing the doubly-terminated 75 load (net 37.5). When no monitor is connected, only the local 75 load is detected and the RIVA128ZX switches to television output mode. The BIOS sets the CRTC registers to generate the appropriate timing for the local television standard and the DACs are adjusted to compensate for the single 75 load. Monitor mode is always selected if a monitor is detected since it is assumed to be the output device of choice, having a higher display fidelity than television. Timing generation Televisions contain two Phase-Locked Loops (PLLs). One PLL locks the horizontal frequency and is used to synchronize horizontal and vertical flyback, and to keep the active video region stable and centered. The second PLL locks the color subcarrier frequency (NTSC 3.5794545MHz or PAL 4.43361875MHz). The color subcarrier is used as a phase reference to extract the color information from the television signal. The RIVA128ZX encodes horizontal and vertical timing on a composite sync signal. Using a 13.5000MHz reference clock, the RIVA128ZX timing generator creates ITU-R-601 NTSC and PAL compliant horizontal timing with only ppm (parts per million) error. The RIVA128ZX does not use
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the color subcarrier clock internally. The reference clock source can be located on the television upgrade module with the video encoder and TV output connectors, thus lowering the base system cost. Flicker filter RIVA128ZX provides an optional flicker filtering feature for TV and interlaced displays. Without flicker filtering, elements of an image present on either the odd or the even field, but not both, are seen to flicker or shimmer obtrusively. This is a problem especially with 1-pixel-wide horizontal lines often originating from computer generated GUI displays. Flicker filtering causes a slight smearing of pixels in the vertical direction. This trades off image quality versus flicker. The displayed pixel contains a proportion of the data for the pixel on that line, plus a smaller proportion of the data of the equivalent pixel on the line above and on the line below. Overall, the proportions add up to 1 so that the brightness of the screen does not alter and the pixel data does not get clipped. Flicker filtering only takes place on pixel data from the framestore - the pattern written into the cursor already has flicker removed. No flicker removal is performed on video images. Overscan and underscan The RIVA128ZX supports overscan and underscan in the horizontal and vertical directions using hardware scaling. Underscan allows 640x480 resolution to fit onto NTSC displays and 800x600 resolution to fit onto PAL displays. Scaling can be adjusted and controlled by software to suit specific TV requirements. The TV output image position is also software controllable.
128-BIT 3D MULTIMEDIA ACCELERATOR
12 IN-CIRCUIT BOARD TESTING
RIVA128ZX
The RIVA128ZX has a number of features designed to support in-circuit board testing. These include: * Dedicated test mode input and dual-function test mode select pins selecting the following modes: - Pin float - Parametric NAND tree - All outputs driven high - All outputs driven low * Checksum test * Test registers 12.1 TEST MODES Primary test control is provided by the dedicated TESTMODE input pin. The RIVA128ZX is in normal operating mode when this pin is deasserted. When TESTMODE is asserted, MP_AD[3:0] are reassigned as TESTCTL[3:0] respectively. Test modes are selected asynchronously through a combination of the pin states shown in Table 21. Table 21. Test mode selection and descriptions
Test mode 3 Parametric NAND tree 1 TESTCTL[3:0] 2 0 1 1 0 0 A single parametric NAND tree is provided to give a quiescent environment in which to test VIL and VIH without requiring core activity. This capability is provided in the pads by chaining all I and I/O paths together via two input NAND gates. The chain begins with one input of the first NAND gate tied to VDD while the other input is connected to the first device pin on the NAND tree. The output of this gate then becomes the input of the next NAND gate in the tree and so on until all pad input paths have been connected. The final NAND gate output is connected to an output-only pin whose normal functionality is disabled in NAND tree mode. The NAND tree length is therefore equal to the number of I and I/O pins in the RIVA128ZX. Output -only pins are not connected into the NAND tree. Pin float Outputs high Outputs low 1 1 1 1 1 1 0 1 1 0 0 1 All pin output drivers are tristated in this test mode so that pin leakage current (IIL,IIH,IOZL,IOZH) can be measured. All pin output drivers drive a high output state in this test mode so that output high voltage (VOH at IOH) can be measured. All pin output drivers drive a low output state in this test mode so that output low voltage (VOL at IOL) can be measured. Description
12.2 CHECKSUM TEST
The RIVA128ZX hardware checksum feature supports testing of the entire pixel datapath at full video rates from the framebufferthrough to the DAC inputs. Each of the three RGB colors can be tested to provide a correlation between the intended and actual display. Checksums are accumulated during active (unblanked) display. Note that the checksum mechanism does not check the DAC outputs (i.e. what is physically being displayed on the monitor). For a given image (which can be a real application's image or a specially prepared test card), theoretically derived checksum values can be calculated for a
selected RGB color, which are then compared with the RIVA128ZX hardware checksum value. Alternatively the checksum value from a known good chip can be used as the reference. Hardware checksum accumulation is not affected by the horizontal and vertical synchronization waveforms or timings. Any discrepancy between the calculated and RIVA128ZX hardware accumulated checksum values therefore indicates a problem in the device or system being tested. Details of programming the RIVA128ZX checksum are given in the RIVA128ZX Programming Reference Manual [2].
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RIVA128ZX
13 ELECTRICAL SPECIFICATIONS
Parameter DC supply voltage Voltage on input and output pins TS TA Storage temperature (ambient) Temperature under bias Analog output current (per output) DC digital output current (per output)
NOTES 1
128-BIT 3D MULTIMEDIA ACCELERATOR
13.1 ABSOLUTE MAXIMUM RATINGS1
Symbol VDD/AVDD Min. Max. 3.6 GND-1.0 -55 0 VDD+0.5 125 85 45 25 V V C C mA mA 2 Units Notes
2
Stresses greater than those listed under `Absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. For 3V tolerant pins VDD = 3.3V 0.3V, for 5V tolerant pins (PCI, Video Port and Serial interfaces) VDD = 5V 0.5V
13.2 OPERATING CONDITIONS
Symbol TC Parameter Case temperature Min. Typ. Max. 120 Units C Notes
13.3 DC SPECIFICATIONS Table 22. DC characteristics
Symbol VDD IIN Parameter Positive supply voltage Input current (signal pins) Power dissipation
NOTES 1 2 Includes high impedance output leakage for all bi-directional buffers with tri-state outputs VDD = max, GND VIN VDD
Min. 3.135
Typ. 3.3
Max. 3.465 10 3.7
Units V A W
Notes 1, 2
Table 23. Parameters applying to PCI and AGP interface pins
Symbol CIN COUT VIH VIL VOH VOL IOH IOL Parameter Input capacitance Output load capacitance Input logic 1 voltage Input logic 0 voltage Output logic 1 level Output logic 0 level Output load current, logic 1 level Output load current, logic 0 level Min. 5 5 2.0 -0.5 2.4 0.55 -2 3 or 6 Typ. Max. 10 50 5.75 0.8 Units pF pF V V V V mA mA 2 Notes 1 1
Parameters for 5V signaling environment only:
Parameters for 3.3V and AGP signaling environments only: VIH Input logic 1 voltage 0.475VDD VDD+0.5 V
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128-BIT 3D MULTIMEDIA ACCELERATOR
Symbol VIL VOH VOL IOH IOL
NOTE 1 2
RIVA128ZX
Typ. Max. 0.325VDD Units V V 0.1VDD -0.5 1.5 V mA mA Notes
Parameter Input logic 0 voltage Output logic 1 level Output logic 0 level Output load current, logic 1 level Output load current, logic 0 level
Min. -0.5 0.9VDD
Tested but not guaranteed. 3mA for all signals except PCIFRAME#, PCITRDY#, PCIIRDY#, PCIDEVSEL# and PCISTOP# which have IOL of 6mA.
13.4 ELECTRICAL SPECIFICATIONS Table 24. Parameters applying to all signal pins except PCI/AGP interfaces
Symbol CIN COUT VIH VIL VOH VOL IOH IOL
NOTE 1 2 Tested but not guaranteed. For 3V tolerant pins VDD = 3.3V 0.3V, for 5V tolerant pins (Video Port and Serial interfaces) VDD = 5V 0.5V
Parameter Input capacitance Output load capacitance Input logic 1 voltage Input logic 0 voltage Output logic 1 level Output logic 0 level Output load current, logic 1 level Output load current, logic 0 level
Min.
Typ. 10 10
Max. 12 50 VDD+0.5 0.8
Units pF pF V V V
Notes 1 1 2
2.0 -0.5 2.4
0.4 -1 1
V mA mA
13.5 DAC CHARACTERISTICS
Parameter Resolution DAC operating frequency White relative to Black current DAC to DAC matching Integral linearity Differential linearity DAC output voltage DAC output impedance Risetime (black to white level) Settling time (black to white) Glitch energy Comparator trip voltage Comparator settling time Internal Vref voltage Internal Vref voltage accuracy 1.235 3 5 280 50 335 20 1 3 5.9 100 420 100 16.74 17.62 1 0.5 0.25 Min. Typ. 10 250 18.50 2.5 1.5 1 1.2 Max. Units bits MHz mA % LSB8 LSB8 V k ns ns pVs mV s V % 2,5,6 2,5,7 2,5 2 2,4 2,3,8 2,3,8 2 Notes
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RIVA128ZX
NOTES 1 2 3 4 5 6 7 8
128-BIT 3D MULTIMEDIA ACCELERATOR
Blanking pedestals are not supported in TV output mode. VREF = 1.235V, RSET = 147 LSB8 = 1 LSB of 8-bit resolution DAC About the midpoint of the distribution of the three DACs 37.5ohm, 30pF load 10% to 90% Settling to within 2% of full scale deflection Monotonicity guaranteed
13.6 FREQUENCY SYNTHESIS CHARACTERISTICS
Parameter XTALIN crystal frequency range Internal VCO frequency Memory clock output frequency Pixel clock output frequency Pixel clock output frequency (video displayed) Synthesizer lock time
NOTE 1 2 3 A series resonant crystal should be connected to XTALIN The pixel clock can be programmed to within 0.5% of any target frequency 10 fpixclk 250MHz The maximum pixel clock frequency when the RIVA128ZX is displaying full motion video
Min 4 128
Typ.
Max 15 256 100 250 110 500
Units MHz MHz MHz MHz MHz s
Notes 1
2 3
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128-BIT 3D MULTIMEDIA ACCELERATOR
14 PACKAGE DIMENSION SPECIFICATION
RIVA128ZX
14.1 300 PIN BALL GRID ARRAY PACKAGE Figure 69. RIVA128ZX 300 Plastic Ball Grid Array Package dimension reference
0.250 C
D2 Pin 1 indicator
A1
0.350 C
20 19 18 17 16 15 14 13 12 11 10 9 8 7
654321 A B C D E F G H J K L M N P R T U V W Y
e
E2
E1
E
e
e
A2 C 0.300 S C A S B S 0.100 S C SOLDER BALL (Typ) b A
0.150 C
e B D1 A
0.200
D
(4x)
All dimensions in mm unless otherwise noted tolerances unless otherwise noted (mm) 0 10 0.05 >10 50 0.1 >50 200 0.15 >200 0.25
Table 25. RIVA128ZX 300 Plastic Ball Grid Array Package dimension specification
Ref. A A1 A2 b D D1 D2 e E E1 E2 1.27 Basic 27.00 24.13 Basic 23.90 24.10 26.82 27.18 27.00 24.13 Basic 23.90 24.10 0.050 Basic 1.063 0.951 Basic 0.941 0.949 1.055 1.070 Millimeters Typ. Min. 2.125 0.50 1.625 0.60 26.82 Max. 2.595 0.70 1.895 0.90 27.18 1.063 0.951 Basic 0.941 0.949 Typ. Inches Min. 0.083 0.020 0.064 0.024 1.055 Max. 0.102 0.027 0.074 0.035 1.070
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RIVA128ZX
15 REFERENCES
128-BIT 3D MULTIMEDIA ACCELERATOR
1 RIVA128ZX Turnkey Manufacturing Package TMP, Design Guide, NVIDIA Corp./STMicroelectronics 2 RIVA128ZX Programming Reference Manual, NVIDIA Corp./STMicroelectronics
3 Accelerated Graphics Port Interface Specification, Revision 1.0, Intel Corporation, July 1996 4 PCI Local Bus Specification, revision 2.1, PCI Special Interest Group, June 1995 5 Recommendation 656 of the CCIR, Interfaces for digital component video signals in 525-line and 625line television systems, CCIR, 1990
6 Display Data Channel (DDCTM) standard, Version 2.0, revision 0, Video Electronics Standards Association, April 9th 1996 (Video Electronics Standards Association - http://www.vesa.org) 7 AD722 PAL/NTSC TV Encoder Datasheet, Analog Devices Inc., 1995 8 MK2715 NTSC/PAL Clock Source Datasheet, MicroClock Inc., March 1997 16 ORDERING INFORMATION
Device RIVA128ZX RIVA128ZX Package 300 pin PBGA 300 pin PBGA Supply format Trays Tape and reel Part number STG3005A2S STG3005A2S/TR
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128-BIT 3D MULTIMEDIA ACCELERATOR
APPENDIX
RIVA128ZX
Descriptions of register contents include an indication if register fields are readable (R) or writable (W) and the initial power-on or reset value of the field (I). `-' indicates not readable / writable, X indicates an indeterminate value, hence I=X indicates register or field not reset.
A PCI CONFIGURATION REGISTERS
This section describes the 256 byte PCI configuration spaces as implemented by the RIVA128ZX. A single PCI VGA device is defined by the RIVA128ZX which decodes and acknowledges the first 256 bytes of the configuration address space. The RIVA128ZX does not respond (does not assert DEVSEL#) for functions 1 -7. A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE
Byte offsets 0x03 - 0x00
0x03 0x02 0x01
9 8 VENDOR_ID 7 6 5
0x00
4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DEVICE_ID_CHIP
Device Identification Register (0x03 - 0x02)
Bits 31:16 Function The DEVICE_ID_CHIP bits contain the chip number allocated by the manufacturer to identify the particular device. = 0x0018 if the power-on reset configuration APCI Supported bit = 0 = 0x0019 if the power-on reset configuration APCI Supported bit = 1 RWI R -X
Vendor Identification Register (0x01 - 0x00)
Bits 15:0 Function VENDOR_ID bits allocated by the PCI Special Interest Group to uniquely identify the manufacturer of the device. NVIDIA/STMicroelectronics Vendor ID = 0x12D2 (4818) RWI R -X
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x07 - 0x04
0x07 0x06 0x05
9 8 SERR_ENABLE 7 Reserved 6 5 PALETTE_SNOOP
0x04
4 WRITE_AND_INVA: 3 Reserved 2 BUS_MASTER 1 MEMORY_SPACE 0 IO_SPACE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved SERR_SIGNALLED RECEIVED_MASTER RECEIVED_TARGET Reserved DEVSEL_TIMING Reserved 66MHZ CAP_LIST Reserved Reserved
Device Status Register (0x07 - 0x06)
Bits 31 30 29 Function Reserved SERR_SIGNALLED is set whenever the RIVA128ZX asserts SERR#. RECEIVED_MASTER indicates that a master device's transaction (except for Special Cycle) was terminated with a master-abort. This bit is clearable (=1). 0=No abort 1=Master aborted RECEIVED_TARGET indicates that a master device's transaction was terminated with a target-abort. This bit is clearable (=1). 0=No abort 1=Master received target aborted Reserved The DEVSEL_TIMING bits indicate the timing of DEVSEL#. These bits indicate the slowest time that the RIVA128ZX asserts DEVSEL# for any bus command except Configuration Read and Configuration Write. The RIVA128ZX responds with medium DEVSEL# for VGA, memory and I/O accesses. For accesses to the 16MByte memory ranges described by the BARs, the chip responds with fast decode (no wait states). 00=fast 01=medium Reserved 66MHZ indicates that the RIVA128ZX is capable of 66MHz operation. This bit reflects the latched state of the 66MHz/33MHz strap option. CAP_LIST indicates that there is a linked list of registers containing information about new capabilities not available within the original PCI configuration structure. This bit indicates that the (byte) Capability Pointer Register located at 0x34 points to the start of this linked list. The value of CAP_LIST depends on the RIVA128ZX power-on reset configuration Host Interface and ACPI Supported settings: 0 = Host Interface is PCI and ACPI not supported 1= Host interface is AGP or ACPI supported Reserved RWI R-0 RW0 RW0
28
RW0
27 26:25
R-0 R-1
24:22 21 20
R-0 R-1 R -X
19:16
R-0
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128-BIT 3D MULTIMEDIA ACCELERATOR
Command Register (0x05 - 0x04)
Bits 15:9 8 Function Reserved SERR_ENABLE is an enable bit for the SERR# driver. 0=Disables the SERR# driver 1=Enables the SERR# driver Reserved PALETTE_SNOOP indicates that VGA compatible devices should snoop their palette registers. 0=Palette accesses treated like all other accesses 1=Enables special palette snooping behavior WRITE_AND_INVAL is an enable bit for using the Memory Write and Invalidate command. 1=The RIVA128ZX as bus master may generate the command 0=The Memory Write command must be used instead of Memory Write and Invalidate Reserved BUS_MASTER indicates that the device can act as a master on the PCI bus. 0=Disables the RIVA128ZX from generating PCI accesses 1=Allows the RIVA128ZX to behave as a bus master MEMORY_SPACE indicates that the RIVA128ZX will respond to memory space accesses. 0=Device response disabled 1=Enables response to Memory space accesses. The device will decode and respond to the 16MByte ranges as well as the default VGA memory range when it is enabled. The VGA decode range may change based upon the value in the VGA graphics Miscellaneous Register GR06, bits[3:2] and other enable bits, see RIVA128ZX Programming Reference Manual [2]. IO_SPACE indicates that the device will respond to I/O space accesses. This bit enables I/O space accesses for the VGA function as defined in the PCI specification. These include 0x3B0 - 0x3BB, 0x3C0 - 0x3DF and their aliases.
RIVA128ZX
RWI R-0 RW0
7:6 5
R-0 RW0
4
RW0
3 2
R-0 RW0
1
RW0
0
RW0
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x0B - 0x08
0x0B 0x0A 0x09
9 8 7 6 5
0x08
4 REVISION_ID 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CLASS_CODE
Class Code Register (0x0B - 0x09)
Bits 31:8 Function The CLASS_CODE bits identify the generic function of the device and (in some cases) a specific register-level programming interface. The register is broken into three byte-size fields. The upper byte (at offset 0x0B) is a base class code which broadly classifies the type of function the device performs. The middle-byte (at offset 0x0A) is a sub-class code which identifies more specifically the function of the device. The lower byte (at offset 0x09) identifies a specific register-level programming interface (if any) so that device independent software can interact with the device. The VGA function responds as a VGA compatible controller. 0x030000=VGA compatible controller RWI R -X
Revision Identification Register (0x08)
Bits 7:0 Function The REVISION_ID bits specify a device specific revision identifier. The value is chosen by the vendor. This field should be vie wed as a vendor defined extension to the DEVICE_ID. 0x01=Revision B RWI R-X
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x0F - 0x0C
0x0F 0x0E 0x0D
9 8 Reserved 7 6 5
0x0C
4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved HEADER_TYPE
Bits 31:24 23:16
Function Reserved HEADER_TYPE identifies the device as single or multi-function. RIVA128ZX responds as a single-function device. 0x00=Single function device Reserved
RWI R-0 R - 0x00
16:00
R-0
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x13 - 0x10
0x13 0x12 0x11
9 8 7 6 5
0x10
4 3 PREFETCHABLE 2 ADDRESS_TYPE 1 0 SPACE_TYPE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BASE_ADDRESS BASE_RESERVED
Base Memory Address Register (0x13 - 0x10)
Bits 31:24 Function The BASE_ADDRESS bits contain the most significant bits of the base address of the device. This indicates that the RIVA128ZX requires a 16MByte block of contiguous memory beginning on a 16MByte boundary. This memory range contains memory-mapped registers and FIFOs and should not be set as part of a PentiumProTM's write combining range. The BASE_RESERVED bits form the least significant bits of the base address and are hardwired to 0. The PREFETCHABLE bit indicates that there are no side effects on reads, that the device returns all bytes on reads regardless of the byte enables, and that host bridges can merge processor writes into this range without causing errors. The ADDRESS_TYPE bits contain the type (width) of the Base Address. 0=32-bit The SPACE_TYPE bit indicates whether the register maps into Memory or I/O space. 0=Memory space RWI RW0
23:4 3
R-0 R-1
2:1 0
R-0 R-0
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x17 - 0x14
0x17 0x16 0x15
9 8 7 6 5
0x14
4 3 PREFETCHABLE 2 ADDRESS_TYPE 1 0 SPACE_TYPE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BASE_ADDRESS BASE_RESERVED
Base Memory Address Register (0x17 - 0x14)
Bits 31:24 Function The BASE_ADDRESS bits contain the most significant bits of the base address of the device. This indicates that the RIVA128ZX requires a 16MByte block of contiguous memory beginning on a 16MByte boundary. This memory range contains linear frame buffer access and may be set as part of a PentiumProTM's write combining (wc) range. The BASE_RESERVED bits form the least significant bits of the base address and are hardwired to 0. The PREFETCHABLE bit indicates that there are no side effects on reads, that the device returns all bytes on reads regardless of the byte enables, and that host bridges can merge processor writes into this range without causing errors. The ADDRESS_TYPE bits contain the type (width) of the Base Address. 0=32-bit The SPACE_TYPE bit indicates whether the register maps into Memory or I/O space. 0=Memory space RWI RW0
23:4 3
R-0 R-1
2:1 0
R-0 R-0
Byte offsets 0x2B - 0x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x00000000 9 8 7 6 5 4 3 2 1 0
Base Address Registers (0x2B - 0x18)
Bits 31:0 Function These bits are hardwired (read-only) to 0. RWI R-0
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x2F - 0x2C
0x2F 0x2E 0x2D
9 8 SUB_VENDOR_ID 7 6 5
0x2C
4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SUBSYSTEM_ID
Subsystem Vendor ID (0x2F - 0x2C)
Bits 31:16 15:0 Function SUBSYSTEM_ID is a unique code defined by the vendor to identify this product. SUB_VENDOR_ID bits allocated by the PCI Special Interest Group to uniquely identify the manufacturer of the sub-system. Based on the strapping options read from ROM during PCI reset, this field may behave in one of two ways: 1 These bytes can be read from address locations 0x54 - 0x57 of the ROM BIOS automatically during reset. This is useful for add-in card implementations. 2 These bytes may be written from PCI configuration space at locations 0x40 - 0x43. RWI R-0 R-0
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x33 - 0x30
0x33 0x32 0x31
9 8 7 6 Reserved 5
0x30
4 3 2 1 0 ROM_DECODE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ROM_BASE_ADDRESS ROM_BASE_RESERVED
Expansion ROM Base Address Register (0x33 - 0x30)
Bits 31:22 Function The ROM_BASE_ADDR bits contain the base address of the Expansion ROM. The bits correspond to the upper bits of the Expansion ROM base address. This decode permits the PCI boot manager to place the expansion ROM on a 4MByte boundary. RIVA128ZX currently maps a 64KByte BIOS into the bottom of this 4MByte range. Typically the first 32K of this ROM contains the VGA BIOS code as well as the PCI BIOS Expansion ROM Header and Data Structure. ROM_BASE_RESERVED contain the lower bits of the base address of the Expansion ROM. These bits are hardwired to 0, forcing a 4MByte boundary. Reserved The ROM_DECODE bit indicates whether or not the RIVA128ZX accepts accesses to its expansion ROM. When the bit is set, address decoding is enabled using the parameters in the other part of the base register. The MEMORY_SPACE bit (PCI Configuration Register 0x04, page 70) has precedence over the ROM_DECODE bit. RIVA128ZX will respond to accesses to its expansion ROM only if both the MEMORY_SPACE bit and the ROM_DECODE bit are set to 1. 0=Expansion ROM address space is disabled 1=Expansion ROM address decoding is enabled RWI RWX
21:11 10:1 0
R-0 R-0 RW0
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x37 - 0x34
0x37 0x36 0x35
9 8 7 6 5
0x34
4 CAP_PTR 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved
Capabilities Pointer Register (0x37 - 0x34)
Bits 31:8 7:0 Function Reserved This field contains a byte offset into this PCI configuration space containing the first item in the capabilities list. The offset returned depends on the RIVA128ZX power-on reset configuration Host Interface and ACPI Supported settings: CAP_PTR = 0x0 if Host Interface is PCI and APCI not supported CAP_PTR = 0x44 if Host Interface is AGP and APCI not supported CAP_PTR = 0x60 if APCI supported RWI R-0 R -X
Byte offsets 0x3B - 0x38
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0x00000000 9 8 7 6 5 4 3 2 1 0
Reserved (0x3B - 0x38)
Bits 31:0 Function These bits are reserved and hardwired (read-only) to 0. RWI R-0
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offset 0x3F - 0x3C
0x3F 0x3E 0x3D
9 8 7 6 5
0x3C
4 INTERRUPT_LINE 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MAX_LAT MIN_GNT INTERRUPT_PIN
MAX_LAT Register (0x3F)
Bits 31:24 Function The MAX_LAT bits contain the maximum time the RIVA128ZX requires to gain access to the PCI bus. This read-only register is used to specify the RIVA128ZX's desired settings for Latency Timer values. The value specifies a period of time in units of 250ns. 1=250ns RWI R-1
MIN_GNT Register (0x3E)
Bits 23:16 Function The MIN_GNT bits contain the length of the burst period the RIVA128ZX needs, assuming a clock rate of 33MHz. This read-only register is used to specify the RIVA128ZX's desired settings for Latency Timer values. The value specifies a period of time in units of 250ns. 3=750ns RWI R-3
Interrupt Pin Register (0x3D)
Bits 15:8 Function The INTERRUPT_PIN bits contain the interrupt pin the device (or device function) uses. A value of 1 corresponds to INTA#. RWI R-1
Interrupt Line Register (0x3C)
Bits 7:0 Function The INTERRUPT_LINE bits contain the interrupt routing information. POST software will write the routing information into this register as it initializes and configures the system. The value in this field indicates which input of the system interrupt controller(s) the RIVA128ZX's interrupt pin is connected to. Device drivers and operating systems can use this information to determine priority and vector information. INTERRUPT_LINE is initialized to 0xFF (no connection) at reset. 0=Interrupt line IRQ0 1=Interrupt line IRQ1 0xF=Interrupt line IRQ15 0xFF=No interrupt line connection (reset value) RWI R W 0xFF
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x43 - 0x40
0x43 0x42 0x41
9 8 SUB_VENDOR_ID 7 6 5
0x40
4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SUBSYSTEM_ID
Writeable Subsystem Vendor ID (0x43 - 0x40)
Bits 31:16 Function This SUBSYSTEM_ID field is aliased at 0x2F - 0x2E where it is read-only. It may be modified by System BIOS for systems which do not have a ROM on the RIVA128ZX data pins. This will ensure valid data before enumeration by the operating system. This SUB_VENDOR_ID field is aliased at 0x2D - 0x2C where it is read-only. It may be modified by System BIOS for systems which do not have a ROM on the RIVA128ZX data pins. This will ensure valid data before enumeration by the operating system. RWI RW0
15:0
RW0
Byte offsets 0x47 - 0x44
0x47 0x46 0x45
9 8 7 6 5
0x44
4 CAP_ID 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved MAJOR MINOR NEXT_PTR
Capabilities Identifier Register (Offset = 0x47 - 0x44 = CAP_PTR)
Bits 31:24 23:20 Function Reserved = 0x00 This field indicates the Major revision number of the AGP specification that the RIVA128ZX conforms to. = 0x01 This field indicates the Minor revision number of the AGP specification that the RIVA128ZX conforms to. = 0x00 NEXT_PTR contains the pointer to the next item in the capabilities list. This is the last entry in the capabilities list, hence it contains a null pointer = 0x00. The CAP_ID field identifies the type of capability. AGP = 0x02 RWI R-0 R - 0x01
19:16
R - 0x00
15:8 7:0
R - 0x00 R - 0x02
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x4B - 0x48
0x4B 0x4A 0x49
9 SBA 8 7 6 5 Reserved
0x48
4 3 2 1 RATE 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RQ Reserved
AGP Status Register (0x4B - 0x48 = CAP_PTR+4)
Bits 31:24 Function The RQ field contains the maximum number of AGP command requests this device can have outstanding. RQ = 0x04 Reserved SBA indicates whether the RIVA128ZX supports sideband addressing. 0 = Sideband addressing not supported Reserved RATE indicates the data transfer rate(s) supported by the RIVA128ZX. 11 = 66MHz 1x supported; 133MHz 2x supported RWI R - 0x04
23:10 9 8:2 1:0
R-0 R-0 R-0 R - 0x11
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x4F - 0x4C
0x4F 0x4E 0x4D
9 SBA_ENABLE 8 AGP_ENABLE 7 6 5 Reserved
0x4C
4 3 2 1 DATA_RATE 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RQ_DEPTH Reserved
AGP Command Register (0x4F - 0x4C = CAP_PTR + 8)
Bits 31:24 23:10 9 8 Function This field is set to the minimum request depth of the target as reported in its RQ field. Reserved SBA_ENABLE enables sideband addressing when set. The RIVA128ZX does not implement sideband addressing. AGP_ENABLE allows the RIVA128ZX to act as an AGP master and initiate AGP operations. The target must be enabled before enabling the RIVA128ZX 0 = disabled 1 = AGP operations enabled Reserved The DATA_RATE field must be set to 0x01 to indicate 66MHz /1x transfer mode or 0x02 for 133MHz/2x transfer mode. This value must also be set on the target before being enabled. The initial value 0x00 indicates PCI operation. RWI RWR-0 R-0 RW0
7:3 2:0
R-0 R W 0x00
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
Byte offsets 0x63 - 0x60
0x63 0x62 0x61
9 8 7 6 5
0x60
4 CAP_ID 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved VERSION NEXT_PTR
Power Management Capabilities Register (0x63 - 0x60)
Bits 31:19 18:16 15:8 Function Reserved VERSION indicates that RIVA128ZX is compliant with Revision 1.0 of the PCI Power Management Interface Specification. NEXT_PTR indicates the offset for the next item in the capability list. If the power-on reset configuration Host Interface bit indicates PCI then NEXT_PTR will be null (0x00), indicating there are no further items. If the power-on reset configuration indicates AGP then NEXT_PTR will indicate the next item's offset (the AGP capability, 0x44). A value of `1' read back from CAP_ID indicates this is the Power Management Register. RWI R-0 R-1 R -X
7:0
R-1
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RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x67 - 0x64
0x67 0x66 0x65
9 8 7 6 5
0x64
4 3 2 1 POWER_STATE 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved
Power Management Control/Status Register (0x67 - 0x64)
Bits 31:2 1:0 Function Reserved POWER_STATE indicates and controls the current power state of RIVA128ZX. Two power states are supported D0 (full power) and D3hot (low power). 0x0 = D0 0x3 = D3hot The RIVA128ZX does not physically change its power consumption when POWER_STATE is modified. The device can be transitioned from D3 to D0 either by writing to this register or by applying a hard reset to the PCIRST# pin. RWI R-0 RW0
Byte offset 0xFF - 0x50
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved = 0x00000000
9
8
7
6
5
4
3
2
1
0
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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
85
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. . RIVA 128 and RIVA128ZX are trademarks of STMicroelectronics and NVIDIA Corp. Microsoft, Windows and the Windows logo are registered trademarks of Microsoft Corporation All other products mentioned in this document are trademarks or registered trademarks of their respective owners. (c)1998 STMicroelectronics Inc. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. Document number: 7071857 00
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